Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10394993 | Discretizing gate sizes during numerical synthesis | Mahesh A. Iyer | 2019-08-27 |
| 9519740 | Determining optimal gate sizes by using a numerical solver | Mahesh A. Iyer | 2016-12-13 |
| 9454626 | Solving an optimization problem using a constraints solver | Mahesh A. Iyer | 2016-09-27 |
| 9430442 | Solving a gate-sizing optimization problem using a constraints solver | Mahesh A. Iyer | 2016-08-30 |
| 9384309 | Global timing modeling within a local context | Mahesh A. Iyer, Rajnish Prasad | 2016-07-05 |
| 9280625 | Incremental slack margin propagation | Mahesh A. Iyer | 2016-03-08 |
| 9171122 | Efficient timing calculations in numerical sequential cell sizing and incremental slack margin propagation | Mahesh A. Iyer | 2015-10-27 |
| 9064073 | Hyper-concurrent optimization over multi-corner multi-mode scenarios | Mahesh A. Iyer | 2015-06-23 |
| 9047426 | Performing scenario reduction in a circuit design flow | — | 2015-06-02 |
| 8990750 | Numerical area recovery | Mahesh A. Iyer | 2015-03-24 |
| 8977999 | Numerical delay model for a technology library cell type | Mahesh A. Iyer | 2015-03-10 |
| 8966430 | Robust numerical optimization for optimizing delay, area, and leakage power | Mahesh A. Iyer | 2015-02-24 |
| 8949764 | Excluding library cells for delay optimization in numerical synthesis | Mahesh A. Iyer | 2015-02-03 |
| 8843871 | Estimating optimal gate sizes by using numerical delay models | Mahesh A. Iyer | 2014-09-23 |
| 8826218 | Accurate approximation of the objective function for solving the gate-sizing problem using a numerical solver | Mahesh A. Iyer | 2014-09-02 |
| 8826217 | Modeling gate size range by using a penalty function in a numerical gate sizing framework | Mahesh A. Iyer | 2014-09-02 |
| 8799843 | Identifying candidate nets for buffering using numerical methods | Mahesh A. Iyer | 2014-08-05 |
| 8762905 | Numerical delay model for a technology library cell | Mahesh A. Iyer | 2014-06-24 |
| 8707241 | Performing scenario reduction using a dominance relation on a set of corners | Mahesh A. Iyer | 2014-04-22 |
| 8707242 | Optimizing a circuit design for delay using load-and-slew-independent numerical delay models | Mahesh A. Iyer | 2014-04-22 |
| 8683408 | Sequential sizing in physical synthesis | Mahesh A. Iyer | 2014-03-25 |
| 8621405 | Incremental elmore delay calculation | Mahesh A. Iyer | 2013-12-31 |
| 8589846 | Modeling transition effects for circuit optimization | Mahesh A. Iyer | 2013-11-19 |
| 8418116 | Zone-based optimization framework for performing timing and design rule optimization | Robert Walker, Mahesh A. Iyer | 2013-04-09 |
| 8413099 | Performing scenario reduction | Rajinish K. Prasad | 2013-04-02 |