Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JB

James Beausang — 11 Patents

SYSynopsys: 11 patents #81 of 2,302Top 4%
Mountain View, CA: #1,996 of 11,022 inventorsTop 20%
California: #56,011 of 386,348 inventorsTop 15%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
James Beausang has been granted 11 US patents while listed as an inventor at Synopsys. The first was granted in 1997 and the most recent in September 2002. James Beausang ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list James Beausang in Mountain View, CA, US.

Patents per Year

Patents granted per year, 1997 to 2002Bar chart with a peak of 4 patents in 2000.peak 41997: 2 patents19971998: 2 patents19981999: 2 patents19992000: 4 patents20002002: 1 patents2002

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6449755 Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker Harbinder Singh 2002-09-10 $15,275,000
6141790 Instructions signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker Harbinder Singh 2000-10-31 $32,357,000
6106568 Hierarchical scan architecture for design for test applications Chris Ellingham, Markus F. Robinson, Robert Walker 2000-08-22 $33,109,000
6067650 Method and apparatus for performing partial unscan and near full scan within design for test applications Kenneth D. Wagner, Robert Walker 2000-05-23 $38,837,000
6012155 Method and system for performing automatic extraction and compliance checking of an IEEE 1149.1 standard design within a netlist Harbinder Singh 2000-01-04 $26,240,000
5949692 Hierarchical scan architecture for design for test applications Chris Ellingham, Markus F. Robinson, Robert Walker 1999-09-07 $27,713,000
5903466 Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design Chris Ellingham, Robert Walker 1999-05-11 $15,026,000
5831868 Test ready compiler for design for test synthesis Robert Walker 1998-11-03 $40,458,000
5828579 Scan segment processing within hierarchical scan architecture for design for test applications 1998-10-27 $37,331,000
5703789 Test ready compiler for design for test synthesis Robert Walker 1997-12-30 $28,047,000
5696771 Method and apparatus for performing partial unscan and near full scan within design for test applications Kenneth D. Wagner, Robert Walker 1997-12-09 $16,759,000