Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8450199 | Integrating diverse transistors on the same wafer | Fausto Piazza | 2013-05-28 |
| 7910978 | Process for manufacturing a memory device integrated on a semiconductor substrate and comprising nanocrystal memory cells and CMOS transistors | — | 2011-03-22 |
| 7410872 | Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure | — | 2008-08-12 |
| 7320904 | Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit | Paolo Cappelletti, Paola Zabberoni | 2008-01-22 |
| 7304485 | Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture | Paolo Cappelletti | 2007-12-04 |
| 7078294 | Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure | Emilio Camerlenghi, Daniela Peschiaroli, Paola Zabberoni | 2006-07-18 |
| 7001800 | Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit | Paolo Cappelletti, Paola Zabberoni | 2006-02-21 |
| 6876033 | Electrically erasable and programmable non-volatile memory cell | Paolo Cappelletti, Paolo Ghezzi, Loris Vendrame, Paola Zabberoni | 2005-04-05 |
| 6713347 | Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry | Paolo Cappelletti | 2004-03-30 |
| 6686241 | Method of forming low-resistivity connections in non-volatile memories | Massimo Ati, Nicola Zatelli | 2004-02-03 |
| 6627928 | Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip | Daniela Peschiaroli, Elisabetta Palumbo, Fausto Piazza | 2003-09-30 |
| 6576950 | EEPROM type non-volatile memory cell and corresponding production method | Paolo Cappelletti, Nicola Zatelli | 2003-06-10 |
| 6482698 | Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip | Daniela Peschiaroli, Elisabetta Palumbo, Fausto Piazza | 2002-11-19 |
| 6461922 | METHOD FOR THE INTEGRATION OF RESISTORS AND ESD SELF-PROTECTED TRANSISTORS IN AN INTEGRATED DEVICE WITH A MEMORY MATRIX MANUFACTURED BY MEANS OF A PROCESS FEATURING SELF-ALIGNED SOURCE (SAS) FORMATION AND JUNCTION SALICIDATION | Paolo Colombo | 2002-10-08 |
| 6451653 | MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR CHIP OF AN INTEGRATED CIRCUIT INCLUDING A HIGH-DENSITY INTEGRATED CIRCUIT COMPONENTS PORTION AND A HIGH-PERFORMANCE LOGIC INTEGRATED CIRCUIT COMPONENTS PORTION | — | 2002-09-17 |
| 6410389 | Non-volatile memory cell with a single level of polysilicon, in particular of the flash EEPROM type, and method for manufacturing the same | Paolo Cappelletti, Nicola Zatelli | 2002-06-25 |
| 6410387 | Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry | Paolo Cappelletti | 2002-06-25 |
| 6399442 | Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device | Livio Baldi | 2002-06-04 |
| 6355523 | Manufacturing process for making single polysilicon level flash EEPROM cell | Carlo Riva | 2002-03-12 |
| 6350637 | Method of fabrication of a no-field MOS transistor | Paola Zabberoni | 2002-02-26 |
| 6275960 | Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof | Paolo Cappelletti, Marco Olivo | 2001-08-14 |
| 6188121 | High voltage capacitor | Livio Baldi, Paolo Ghezzi | 2001-02-13 |
| 6181602 | Device and method for reading nonvolatile memory cells | Giovanni Campardo, Rino Micheloni | 2001-01-30 |
| 5936276 | Single polysilicon level flash EEPROM cell and manufacturing process therefor | Carlo Riva | 1999-08-10 |
| 5600590 | Process for the manufacture of an integrated voltage limiter and stabilizer in flash EEPROM memory devices | Paolo Ghezzi | 1997-02-04 |