| 7663927 |
Reading voltage generator for a non-volatile EEPROM memory cell matrix of a semiconductor device and corresponding manufacturing process |
Paola Zuliani, Roberto Annunziata, Daniele Zompi |
2010-02-16 |
| 7456467 |
Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure |
Paola Zuliani, Marina Scaravaggi, Roberto Annunziata |
2008-11-25 |
| 6972454 |
Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure |
Paola Zuliani, Marina Scaravaggi, Roberto Annunziata |
2005-12-06 |
| 6627928 |
Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip |
Daniela Peschiaroli, Alfonso Maurelli, Fausto Piazza |
2003-09-30 |
| 6624471 |
Lateral DMOS transistor with first and second drain electrodes in respective contact with high-and low-concentration portions of a drain region |
Nicola Zatelli, Massimo Atti, Cosimo Torelli |
2003-09-23 |
| 6482698 |
Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip |
Daniela Peschiaroli, Alfonso Maurelli, Fausto Piazza |
2002-11-19 |
| 6319780 |
Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage |
Barbara Crivelli, Daniela Peschiaroli, Nicola Zatelli |
2001-11-20 |