Issued Patents All Time
Showing 101–125 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8026127 | Integrated circuit package system with slotted die paddle and method of manufacture thereof | Byung Tai Do | 2011-09-27 |
| 8021923 | Semiconductor package having through-hole vias on saw streets formed with partial saw | Byung Tai Do, Heap Hoe Kuan | 2011-09-20 |
| 8017501 | Semiconductor package having through-hole vias on saw streets formed with partial saw | Byung Tai Do, Heap Hoe Kuan | 2011-09-13 |
| 8017521 | Semiconductor package having through-hole vias on saw streets formed with partial saw | Byung Tai Do, Heap Hoe Kuan | 2011-09-13 |
| 8003445 | Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof | Reza A. Pagaila, Byung Tai Do | 2011-08-23 |
| 7994624 | Integrated circuit package system with adhesive segment spacer | Byung Tai Do, Reza A. Pagaila | 2011-08-09 |
| 7993979 | Leadless package system having external contacts | Byung Tai Do, Heap Hoe Kuan | 2011-08-09 |
| 7989269 | Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof | Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Rui Huang | 2011-08-02 |
| 7985628 | Integrated circuit package system with interconnect lock | Heap Hoe Kuan, Seng Guan Chow, Dioscoro A. Merilo | 2011-07-26 |
| 7977802 | Integrated circuit packaging system with stacked die and method of manufacture thereof | Reza A. Pagaila, Byung Tai Do | 2011-07-12 |
| 7968979 | Integrated circuit package system with conformal shielding and method of manufacture thereof | Reza A. Pagaila, Byung Tai Do | 2011-06-28 |
| 7952176 | Integrated circuit packaging system and method of manufacture thereof | Reza A. Pagaila, Byung Tai Do | 2011-05-31 |
| 7948066 | Integrated circuit package system with lead locking structure | Byung Tai Do, Heap Hoe Kuan | 2011-05-24 |
| 7923846 | Integrated circuit package-in-package system with wire-in-film encapsulant | Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Rui Huang | 2011-04-12 |
| 7902638 | Semiconductor die with through-hole via on saw streets and through-hole via in active area of die | Byung Tai Do, Heap Hoe Kuan | 2011-03-08 |
| 7872345 | Integrated circuit package system with rigid locking lead | Seng Guan Chow, Heap Hoe Kuan | 2011-01-18 |
| 7843042 | Wafer level integration package | Heap Hoe Kuan, Seng Guan Chow | 2010-11-30 |
| 7829998 | Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer | Byung Tai Do, Heap Hoe Kuan | 2010-11-09 |
| 7829984 | Integrated circuit package system stackable devices | Byung Tai Do, Heap Hoe Kuan | 2010-11-09 |
| 7781261 | Integrated circuit package system with offset stacking and anti-flash structure | Seng Guan Chow, Heap Hoe Kuan | 2010-08-24 |
| 7776655 | Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices | Byung Tai Do, Reza A. Pagaila | 2010-08-17 |
| 7741156 | Semiconductor device and method of forming through vias with reflowed conductive material | Reza A. Pagaila, Byung Tai Do | 2010-06-22 |
| 7709944 | Integrated circuit package system with package integration | Heap Hoe Kuan, Seng Guan Chow, Dioscoro A. Merilo | 2010-05-04 |
| 7659145 | Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device | Byung Tai Do, Heap Hoe Kuan, Reza A. Pagaila | 2010-02-09 |
| 7585750 | Semiconductor package having through-hole via on saw streets formed with partial saw | Byung Tai Do, Heap Hoe Kuan | 2009-09-08 |