Issued Patents All Time
Showing 26–50 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8076779 | Reduction of macro level stresses in copper/low-K wafers | Sey-Shing Sun, Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Hong Ying +1 more | 2011-12-13 |
| 8043968 | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures | Hao Cui, Wilbur G. Catabay | 2011-10-25 |
| 7981757 | Semiconductor component and method of manufacture | Sallie Hose, Sudhama C. Shastri | 2011-07-19 |
| 7928521 | Non-tensioned carbon nanotube switch design and process for making same | Thomas Rueckes, Claude L. Bertin | 2011-04-19 |
| 7915122 | Self-aligned cell integration scheme | Richard J. Carter, Hemanshu Bhatt, Shiqun Gu, James R. B. Elmer, Sey-Shing Sun +2 more | 2011-03-29 |
| 7897462 | Method of manufacturing semiconductor component with gate and shield electrodes in trenches | Duane B. Barber, Brian Pratt | 2011-03-01 |
| 7884430 | Isolated metal plug process for use in fabricating carbon nanotube memory cells | Richard J. Carter, Verne Hornback, Thomas Rueckes, Claude L. Bertin | 2011-02-08 |
| 7829426 | Semiconductor component and method of manufacture | Sallie Hose, Sudhama C. Shastri | 2010-11-09 |
| 7824946 | Isolated metal plug process for use in fabricating carbon nanotube memory cells | Richard J. Carter, Verne Hornback, Claude L. Bertin, Thomas Rueckes | 2010-11-02 |
| 7728433 | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures | Hao Cui, Wilbur G. Catabay | 2010-06-01 |
| 7646077 | Methods and structure for forming copper barrier layers integral with semiconductor substrates structures | Hong-Qiang Lu, Wilbur G. Catabay | 2010-01-12 |
| 7602027 | Semiconductor component and method of manufacture | Sallie Hose, Sudhama C. Shastri | 2009-10-13 |
| 7582566 | Method for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Byung Sung Kwak, Sey-Shing Sun +2 more | 2009-09-01 |
| 7531442 | Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing | Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying +3 more | 2009-05-12 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Byung Sung Kwak, Sey-Shing Sun +2 more | 2008-10-14 |
| 7427563 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures | Hong-Qiang Lu, Wilbur G. Catabay | 2008-09-23 |
| 7402770 | Nano structure electrode design | Sey-Shing Sun, Hemanshu Bhatt, Richard J. Carter | 2008-07-22 |
| 7361965 | Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Byung Sung Kwak, Sey-Shing Sun +2 more | 2008-04-22 |
| 7312532 | Dual damascene interconnect structure with improved electro migration lifetimes | William K. Barth, Hongqiang Lu | 2007-12-25 |
| 7300869 | Integrated barrier and seed layer for copper interconnect technology | Sey-Shing Sun, Byung Sung Kwak | 2007-11-27 |
| 7276441 | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures | Hao Cui, Wilbur G. Catabay | 2007-10-02 |
| 7196420 | Method and structure for creating ultra low resistance damascene copper wiring | Hongqiang Lu, Sey-Shing Sun | 2007-03-27 |
| 7179736 | Method for fabricating planar semiconductor wafers | Byung Sung Kwak, Sey-Shing Sun | 2007-02-20 |
| 7160805 | Inter-layer interconnection structure for large electrical connections | William K. Barth | 2007-01-09 |
| 7115425 | Integrated circuit process monitoring and metrology system | Eric Jacob Jan Kirchner, James R. B. Elmer | 2006-10-03 |