Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11145581 | Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks | Darrell D. Truhitte | 2021-10-12 |
| 11049843 | Semiconductor packages | Phillip Celaya, Robert L. Marquis, Darrell D. Truhitte | 2021-06-29 |
| 10770333 | Wafer level flat no-lead semiconductor packages and methods of manufacture | Darrell D. Truhitte | 2020-09-08 |
| 10770332 | Wafer level flat no-lead semiconductor packages and methods of manufacture | Darrell D. Truhitte | 2020-09-08 |
| 10707111 | Wafer level flat no-lead semiconductor packages and methods of manufacture | Darrell D. Truhitte | 2020-07-07 |
| 10529632 | Damaging components with defective electrical couplings | Darrell D. Truhitte | 2020-01-07 |
| 10304798 | Semiconductor packages with leadframes and related methods | Phillip Celaya, Robert L. Marquis, Darrell D. Truhitte | 2019-05-28 |
| 10269609 | Wafer level flat no-lead semiconductor packages and methods of manufacture | Darrell D. Truhitte | 2019-04-23 |
| 10163766 | Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks | Darrell D. Truhitte | 2018-12-25 |
| 10103072 | Damaging components with defective electrical couplings | Darrell D. Truhitte | 2018-10-16 |
| 9899349 | Semiconductor packages and related methods | Phillip Celaya, Robert L. Marquis, Darrell D. Truhitte | 2018-02-20 |
| 9892952 | Wafer level flat no-lead semiconductor packages and methods of manufacture | Darrell D. Truhitte | 2018-02-13 |
| 8324026 | Method for manufacturing a semiconductor component | Phillip Celaya, Robert L. Marquis | 2012-12-04 |
| 8319323 | Electronic package having down-set leads and method | Joseph K. Fauty, Jay A. Yoder, William F. Burghout | 2012-11-27 |
| 8253239 | Multi-chip semiconductor connector | Francis J. Carney, Phillip Celaya, Joseph K. Fauty, Stephen St. Germain, Jay A. Yoder | 2012-08-28 |
| 8071427 | Method for manufacturing a semiconductor component and structure therefor | Phillip Celaya, Robert L. Marquis | 2011-12-06 |
| 7901990 | Method of forming a molded array package device having an exposed tab and structure | Kent L. Kime, Joseph K. Fauty | 2011-03-08 |
| 7875964 | Multi-chip semiconductor connector and method | Francis J. Carney, Phillip Celaya, Joseph K. Fauty, Stephen St. Germain, Jay A. Yoder | 2011-01-25 |
| 7825505 | Semiconductor package and method therefor | Phillip Celaya | 2010-11-02 |
| 7820528 | Method of forming a leaded molded array package | William F. Burghout, Francis J. Carney, Joseph K. Fauty, Jay A. Yoder | 2010-10-26 |
| 7656048 | Encapsulated chip scale package having flip-chip on lead frame structure | Joseph K. Fauty, Denise Thienpont | 2010-02-02 |
| 7638863 | Semiconductor package and method therefor | Phillip Celaya | 2009-12-29 |
| 7602054 | Method of forming a molded array package device having an exposed tab and structure | Kent L. Kime, Joseph K. Fauty | 2009-10-13 |
| 7598123 | Semiconductor component and method of manufacture | Jay A. Yoder, Joseph K. Fauty | 2009-10-06 |
| 7588999 | Method of forming a leaded molded array package | William F. Burghout, Francis J. Carney, Joseph K. Fauty, Jay A. Yoder | 2009-09-15 |