Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10319680 | Metal contact via structure surrounded by an air gap and method of making thereof | Jongsun Sel, Masaaki Higashitani, Fumiaki Toyama, Peter Rabkin | 2019-06-11 |
| 10304559 | Memory write verification using temperature compensation | Himanshu Hemant Naik, Biswajit Ray, Changyuan Chen | 2019-05-28 |
| 10304551 | Erase speed based word line control | Biswajit Ray, Gerrit Jan Hemink, Changyuan Chen | 2019-05-28 |
| 10269439 | Post write erase conditioning | Changyuan Chen, Biswajit Ray | 2019-04-23 |
| 10115459 | Multiple liner interconnects for three dimensional memory devices and method of making thereof | Katsuo Yamada, Tomoyasu Kakegawa, Peter Rabkin, Jayavel Pachamuthu, Masaaki Higashitani | 2018-10-30 |
| 10074440 | Erase for partially programmed blocks in non-volatile memory | Biswajit Ray, Changyuan Chen | 2018-09-11 |
| 10008273 | Cell current based bit line voltage | Biswajit Ray, Gerrit Jan Hemink, Bijesh Rajamohanan, Changyuan Chen | 2018-06-26 |
| 9972396 | System and method for programming a memory device with multiple writes without an intervening erase | Himanshu Hemant Naik, Changyuan Chen, Biswajit Ray | 2018-05-15 |
| 9935050 | Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof | Yuki Mizutani, Zhenyu Lu | 2018-04-03 |
| 9711231 | System solution for first read issue using time dependent read voltages | Chris Yip, Philip Reusswig, Nian Niles Yang, Grishma Shah, Abuzer Dogan +3 more | 2017-07-18 |
| 9704588 | Apparatus and method for preconditioning currents to reduce errors in sensing for non-volatile memory | Biswajit Ray, Changyuan Chen | 2017-07-11 |
| 9564226 | Smart verify for programming non-volatile memory | Gerrit Jan Hemink, Zhenming Zhou, Masaaki Higashitani | 2017-02-07 |
| 9543028 | Word line dependent temperature compensation scheme during sensing to counteract cross-temperature effect | Biswajit Ray, Changyuan Chen | 2017-01-10 |
| 9449701 | Non-volatile storage systems and methods | Chia-Lin Hsiung, Fumiaki Toyama | 2016-09-20 |
| 9443597 | Controlling dummy word line bias during erase in non-volatile memory | Deepanshu Dutta, Masaaki Higashitani | 2016-09-13 |
| 9396808 | Method and apparatus for program and erase of select gate transistors | Deepanshu Dutta, Yan Li, Masaaki Higashitani | 2016-07-19 |
| 9368222 | Bit line pre-charge with current reduction | Masaaki Higashitani | 2016-06-14 |
| 9349452 | Hybrid non-volatile memory cells for shared bit line | Masaaki Higashitani | 2016-05-24 |
| 9202579 | Compensation for temperature dependence of bit line resistance | Chia-Lin Hsiung, Man Lung Mui, Masaaki Higashitani | 2015-12-01 |
| 9165656 | Non-volatile storage with shared bit lines and flat memory cells | Masaaki Higashitani | 2015-10-20 |
| 9159406 | Single-level cell endurance improvement with pre-defined blocks | Masaaki Higashitani, Jiahui Yuan | 2015-10-13 |
| 9142305 | System to reduce stress on word line select transistor during erase operation | Man Lung Mui, Masaaki Higashitani, Fumiaki Toyama | 2015-09-22 |
| 9082502 | Bit line and compare voltage modulation for sensing nonvolatile storage elements | Masaaki Higashitani | 2015-07-14 |
| 9076544 | Operation for non-volatile storage system with shared bit lines | Nima Mokhlesi, Man Lung Mui | 2015-07-07 |
| 9047971 | Operation for non-volatile storage system with shared bit lines | Nima Mokhlesi, Man Lung Mui | 2015-06-02 |