Issued Patents All Time
Showing 76–100 of 121 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8879333 | Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits | Xiying Costa, Haibo Li, Masaaki Higashitani | 2014-11-04 |
| 8873293 | Dynamic erase voltage step size selection for 3D non-volatile memory | Wendy Ou, Yingda Dong, Masaaki Higashitani | 2014-10-28 |
| 8867271 | Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device | Haibo Li, Xiying Costa, Masaaki Higashitani | 2014-10-21 |
| 8861280 | Erase for 3D non-volatile memory with sequential selection of word lines | Xiying Costa, Seung Yu, Roy E. Scheuerlein, Haibo Li | 2014-10-14 |
| 8842471 | Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition | Hao Thai Nguyen, Juan Lee, Seungpil Lee, Masahide Matsumoto, Jongmin Park +1 more | 2014-09-23 |
| 8830755 | Reducing weak-erase type read disturb in 3D non-volatile memory | Yingda Dong, Hitoshi Miwa | 2014-09-09 |
| 8830745 | Memory system with unverified program step | Changyuan Chen, Seungpil Lee, Yee Lih Koh, Jongmin Park, Hao Thai Nguyen +1 more | 2014-09-09 |
| 8830717 | Optimized configurable NAND parameters | Chris Avila, Yingda Dong | 2014-09-09 |
| 8824211 | Group word line erase and erase-verify methods for 3D non-volatile memory | Xiying Costa, Alex Mak, Johann Alsmeier | 2014-09-02 |
| 8811075 | Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: verify to program transition | Hao Thai Nguyen, Juan Lee, Seungpil Lee, Jongmin Park | 2014-08-19 |
| 8787094 | Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits | Xiying Costa, Haibo Li, Masaaki Higashitani | 2014-07-22 |
| 8755234 | Temperature based compensation during verify operations for non-volatile storage | Ken Oowada, Yingda Dong, Gerrit Jan Hemink, Hao Thai Nguyen, Seungpil Lee +2 more | 2014-06-17 |
| 8743618 | Bit line resistance compensation | Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim | 2014-06-03 |
| 8737132 | Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for NAND flash memory | Hao Thai Nguyen, Juan Lee, Seungpil Lee, Jongmin Park | 2014-05-27 |
| 8670285 | Reducing weak-erase type read disturb in 3D non-volatile memory | Yingda Dong, Hitoshi Miwa | 2014-03-11 |
| 8582381 | Temperature based compensation during verify operations for non-volatile storage | Ken Oowada, Yingda Dong, Gerrit Jan Hemink, Hao Thai Nguyen, Seungpil Lee +2 more | 2013-11-12 |
| 8429330 | Method for scrambling data in which scrambling data and scrambled data are stored in corresponding non-volatile memory locations | Jun Wan, Yupin Fong | 2013-04-23 |
| 8300472 | Low noise sense amplifier array and method for nonvolatile memory | Hao Thai Nguyen, Seungpil Lee | 2012-10-30 |
| 8169831 | High speed sense amplifier array and method for non-volatile memory | Hao Thai Nguyen, Seungpil Lee, Fanglin Zhang, Chi-Ming Wang | 2012-05-01 |
| 8145855 | Built in on-chip data scrambler for non-volatile memory | Jun Wan, Yupin Fong | 2012-03-27 |
| 8116139 | Bit line stability detection | Tien-Chien Kuo | 2012-02-14 |
| 8107298 | Non-volatile memory with fast binary programming and reduced power consumption | Pao-Ling Koh, Tien-Chien Kuo, Khanh Nguyen | 2012-01-31 |
| 8081514 | Partial speed and full speed programming for non-volatile memory using floating bit lines | Yingda Dong, Binh Lee, Deepanshu Dutta | 2011-12-20 |
| 7978526 | Low noise sense amplifier array and method for nonvolatile memory | Hao Thai Nguyen, Seungpil Lee | 2011-07-12 |
| 7974134 | Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory | Fanglin Zhang, Jong Park, Alexander Chu, Seungpil Lee | 2011-07-05 |