Issued Patents All Time
Showing 176–200 of 271 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7351992 | Forming nonvolatile phase change memory cell having a reduced thermal contact area | — | 2008-04-01 |
| 7345907 | Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements | — | 2008-03-18 |
| 7317641 | Volatile memory cell two-pass writing method | — | 2008-01-08 |
| 7307268 | Structure and method for biasing phase change memory array for reliable writing | — | 2007-12-11 |
| 7298665 | Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation | Kenneth So, Luca Fasoli | 2007-11-20 |
| 7280397 | Three-dimensional non-volatile SRAM incorporating thin-film device layer | — | 2007-10-09 |
| 7272052 | Decoding circuit for non-binary groups of memory line drivers | Christopher J. Petti, Luca Fasoli | 2007-09-18 |
| 7259038 | Forming nonvolatile phase change memory cell having a reduced thermal contact area | — | 2007-08-21 |
| 7243203 | Pipeline circuit for low latency memory | — | 2007-07-10 |
| 7233024 | Three-dimensional memory device incorporating segmented bit line memory array | Alper Ilkbahar, Luca Fasoli | 2007-06-19 |
| 7233522 | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same | En-Hsing Chen, Andrew J. Walker, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli | 2007-06-19 |
| 7221588 | Memory array incorporating memory cells arranged in NAND strings | Luca Fasoli, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker | 2007-05-22 |
| 7218570 | Apparatus and method for memory operations using address-dependent conditions | Kenneth So, Luca Fasoli | 2007-05-15 |
| 7219271 | Memory device and method for redundancy/self-repair | Bendik Kleveland, Alper Ilkbahar | 2007-05-15 |
| 7177183 | Multiple twin cell non-volatile memory array and logic block structure and method therefor | Luca Fasoli, Mark G. Johnson | 2007-02-13 |
| 7177169 | Word line arrangement having multi-layer word line segments for three-dimensional memory array | — | 2007-02-13 |
| 7177181 | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics | — | 2007-02-13 |
| 7177191 | Integrated circuit including memory array incorporating multiple types of NAND string structures | Luca Fasoli | 2007-02-13 |
| 7177227 | Transistor layout configuration for tight-pitched memory array lines | Christopher J. Petti, Tanmay Kumar, Abhijit Bandyopadhyay | 2007-02-13 |
| 7142471 | Method and apparatus for incorporating block redundancy in a memory array | Luca Fasoli | 2006-11-28 |
| 7132335 | Semiconductor device with localized charge storage dielectric and method of making same | Alper Ilkbahar, Andrew J. Walker, Luca Fasoli | 2006-11-07 |
| 7106652 | Word line arrangement having multi-layer word line segments for three-dimensional memory array | — | 2006-09-12 |
| 7054219 | Transistor layout configuration for tight-pitched memory array lines | Christopher J. Petti, Tanmay Kumar, Abhijit Bandyopadhyay | 2006-05-30 |
| 7022572 | Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells | N. Johan Knall | 2006-04-04 |
| 7023260 | Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor | Tyler Thorp | 2006-04-04 |