Issued Patents All Time
Showing 151–175 of 271 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7514321 | Method of making three dimensional NAND memory | Nima Mokhlesi | 2009-04-07 |
| 7508714 | Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block | Luca Fasoli, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker | 2009-03-24 |
| 7505321 | Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same | Christopher J. Petti, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Alper Ilkbahar +2 more | 2009-03-17 |
| 7505344 | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics | — | 2009-03-17 |
| 7499304 | Systems for high bandwidth one time field-programmable memory | Christopher J. Petti | 2009-03-03 |
| 7499366 | Method for using dual data-dependent busses for coupling read/write circuits to a memory array | Luca Fasoli | 2009-03-03 |
| 7499355 | High bandwidth one time field-programmable memory | Christopher J. Petti | 2009-03-03 |
| 7495500 | Method for using a multiple polarity reversible charge pump circuit | Ali Al-Shamma | 2009-02-24 |
| 7495947 | Reverse bias trim operations in non-volatile memory | Tanmay Kumar | 2009-02-24 |
| 7492630 | Systems for reverse bias trim operations in non-volatile memory | Tanmay Kumar | 2009-02-17 |
| 7486537 | Method for using a mixed-use memory array with different data states | Christopher J. Petti | 2009-02-03 |
| 7486587 | Dual data-dependent busses for coupling read/write circuits to a memory array | Luca Fasoli | 2009-02-03 |
| 7477093 | Multiple polarity reversible charge pump circuit | Ali Al-Shamma | 2009-01-13 |
| 7474000 | High density contact to relaxed geometry layers | Christopher J. Petti | 2009-01-06 |
| 7465951 | Write-once nonvolatile phase change memory array | — | 2008-12-16 |
| 7463546 | Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders | Luca Fasoli, Christopher J. Petti | 2008-12-09 |
| 7463536 | Memory array incorporating two data busses for memory array block selection | Luca Fasoli, Christopher J. Petti | 2008-12-09 |
| 7450414 | Method for using a mixed-use memory array | — | 2008-11-11 |
| 7447056 | Method for using a multi-use memory cell and memory array | Tanmay Kumar | 2008-11-04 |
| 7433233 | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same | En-Hsing Chen, Andrew J. Walker, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli | 2008-10-07 |
| 7426128 | Switchable resistive memory with opposite polarity write pulses | — | 2008-09-16 |
| 7423304 | Optimization of critical dimensions and pitch of patterned features in and above a substrate | James M. Cleeves | 2008-09-09 |
| 7383476 | System architecture and method for three-dimensional memory | Matthew P. Crowley, Luca Fasoli, Alper Ilkbahar, Mark G. Johnson, Bendik Kleveland +1 more | 2008-06-03 |
| 7362604 | Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements | — | 2008-04-22 |
| 7359279 | Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers | Luca Fasoli | 2008-04-15 |