Issued Patents All Time
Showing 126–150 of 271 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7800933 | Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance | Tanmay Kumar, S. Brad Herner, Christopher J. Petti | 2010-09-21 |
| 7781269 | Triangle two dimensional complementary patterning of pillars | Chun-Ming Wang, Yung-Tin Chen | 2010-08-24 |
| 7773443 | Current sensing method and apparatus for a memory array | — | 2010-08-10 |
| 7773446 | Methods and apparatus for extending the effective thermal operating range of a memory | Tyler Thorp | 2010-08-10 |
| 7764534 | Two terminal nonvolatile memory using gate controlled diode elements | Tyler Thorp | 2010-07-27 |
| 7764549 | Floating body memory cell system and method of manufacture | — | 2010-07-27 |
| 7746680 | Three dimensional hexagonal matrix memory array | Christopher J. Petti | 2010-06-29 |
| 7745265 | Method of making three dimensional NAND memory | Nima Mokhlesi | 2010-06-29 |
| 7732235 | Method for fabricating high density pillar structures by double patterning using positive photoresist | Steven J. Radigan | 2010-06-08 |
| 7733685 | Cross point memory cell with distributed diodes and method of making same | Luca Fasoli | 2010-06-08 |
| 7719874 | Systems for controlled pulse operations in non-volatile memory | Tanmay Kumar | 2010-05-18 |
| 7697366 | Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers | Luca Fasoli | 2010-04-13 |
| 7696812 | Cooperative charge pump circuit and method | Ali Al-Shamma | 2010-04-13 |
| 7667999 | Method to program a memory cell comprising a carbon nanotube fabric and a steering element | S. Brad Herner | 2010-02-23 |
| 7656734 | Methods and apparatus for extending the effective thermal operating range of a memory | Tyler Thorp | 2010-02-02 |
| 7633828 | Hierarchical bit line bias bus for block selectable memory array | Luca Fasoli | 2009-12-15 |
| 7596050 | Method for using a hierarchical bit line bias bus for block selectable memory array | Luca Fasoli | 2009-09-29 |
| 7575973 | Method of making three dimensional NAND memory | Nima Mokhlesi | 2009-08-18 |
| 7570523 | Method for using two data busses for memory array block selection | Luca Fasoli, Christopher J. Petti | 2009-08-04 |
| 7554832 | Passive element memory array incorporating reversible polarity word line and bit line decoders | Luca Fasoli, Christopher J. Petti | 2009-06-30 |
| 7542338 | Method for reading a multi-level passive element memory cell array | Tyler Thorp, Luca Fasoli | 2009-06-02 |
| 7542370 | Reversible polarity decoder circuit | Tianhong Yan, Luca Fasoli | 2009-06-02 |
| 7542337 | Apparatus for reading a multi-level passive element memory cell array | Tyler Thorp, Luca Fasoli | 2009-06-02 |
| 7525869 | Method for using a reversible polarity decoder circuit | Tianhong Yan, Luca Fasoli | 2009-04-28 |
| 7522448 | Controlled pulse operations in non-volatile memory | Tanmay Kumar | 2009-04-21 |