Issued Patents All Time
Showing 426–450 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9665430 | Memory system with error detection and retry modes of operation | Ely Tsern, Mark A. Horowitz | 2017-05-30 |
| 9653146 | High capacity memory system using standard controller component | Suresh Rajan, Scott C. Best | 2017-05-16 |
| 9652409 | Memory access during memory calibration | Ian Shaeffer | 2017-05-16 |
| 9652176 | Memory controller for micro-threaded memory operations | Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai | 2017-05-16 |
| 9645631 | Optimizing power in a memory device | Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani | 2017-05-09 |
| 9628257 | Communication channel calibration for drift conditions | Richard E. Perego, Craig E. Hampel | 2017-04-18 |
| 9575835 | Error correction in a memory device | Thomas Vogelsang, Suresh Rajan, Ian Shaeffer, Wayne F. Ellis | 2017-02-21 |
| 9571231 | In-band status encoding and decoding using error correction symbols | John Eric Linstadt | 2017-02-14 |
| 9569308 | Reduced-overhead error detection and correction | Brian S. Leibowitz | 2017-02-14 |
| 9569393 | Memory module threading with staggered data transfers | Hongzhong Zheng | 2017-02-14 |
| 9570126 | Memory with deferred fractional row activation | James E. Harris, Thomas Vogelsang, Ian Shaeffer | 2017-02-14 |
| 9570145 | Protocol for refresh between a memory controller and a memory device | Brent Haukness | 2017-02-14 |
| 9570196 | Testing through-silicon-vias | Thomas Vogelsang, William N. Ng | 2017-02-14 |
| 9563556 | Techniques for storing data and tags in different memory arrays | — | 2017-02-07 |
| 9563597 | High capacity memory systems with inter-rank skew tolerance | Ely Tsern, Brian S. Leibowitz, Wayne F. Ellis, Akash Bansal, John Brooks +1 more | 2017-02-07 |
| 9536589 | Low-power source-synchronous signaling | Jared L. Zerbe | 2017-01-03 |
| 9515008 | Techniques for interconnecting stacked dies using connection sites | Ely Tsern, Thomas Vogelsang | 2016-12-06 |
| 9501433 | Semiconductor memory systems with on-die data buffering | Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil | 2016-11-22 |
| 9502096 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Lawrence Lai, Kishore Ven Kasamsetty | 2016-11-22 |
| 9490002 | Reduced refresh power | Brent Haukness, Scott C. Best, Gary B. Bronner | 2016-11-08 |
| 9490009 | Fast read speed memory device | Deepak C. Sekar, Gary B. Bronner | 2016-11-08 |
| 9477547 | Controller device with retransmission upon error | Yuanlong Wang | 2016-10-25 |
| 9472262 | Memory controller | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2016-10-18 |
| 9465961 | Methods and circuits for securing proprietary memory transactions | Brian S. Leibowitz, Pradeep Batra, Trung Diep | 2016-10-11 |
| 9459960 | Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation | Ely Tsern, Mark A. Horowitz | 2016-10-04 |