Issued Patents All Time
Showing 51–75 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9666690 | Integrated circuit and method for fabricating the same having a replacement gate structure | Kisik Choi | 2017-05-30 |
| 9653356 | Methods of forming self-aligned device level contact structures | Chanro Park, Ruilong Xie, Min Gyu Sung | 2017-05-16 |
| 9646884 | Block level patterning process | Chanro Park, Sukwon Hong, Min Gyu Sung | 2017-05-09 |
| 9627535 | Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region | Ruilong Xie, Chanro Park, Min Gyu Sung | 2017-04-18 |
| 9607904 | Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices | Albert S. Lee, Paul R. Besser, Kisik Choi, Edward Haywood, Salil Mujumdar | 2017-03-28 |
| 9601490 | FinFET work function metal formation | Hui Zang | 2017-03-21 |
| 9601387 | Method of making threshold voltage tuning using self-aligned contact cap | Xiuyu Cai, Chanro Park | 2017-03-21 |
| 9603152 | Wireless network channel allocation method for interference avoidance | Tae Sik Nam | 2017-03-21 |
| 9595583 | Methods for forming FinFETS having a capping layer for reducing punch through leakage | Min Gyu Sung | 2017-03-14 |
| 9589836 | Methods of forming ruthenium conductive structures in a metallization layer | Xunyuan Zhang | 2017-03-07 |
| 9552992 | Co-fabrication of non-planar semiconductor devices having different threshold voltages | Min Gyu Sung, Chanro Park, Ruilong Xie | 2017-01-24 |
| 9508604 | Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers | Min Gyu Sung, Chanro Park, Ruilong Xie | 2016-11-29 |
| 9502286 | Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices | Ruilong Xie, Chanro Park, Min Gyu Sung, Andre P. Labonte | 2016-11-22 |
| 9502308 | Methods for forming transistor devices with different source/drain contact liners and the resulting devices | Chanro Park, Ruilong Xie, Min Gyu Sung | 2016-11-22 |
| 9496143 | Metal gate structure for midgap semiconductor device and method of making same | Kisik Choi | 2016-11-15 |
| 9484449 | Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers | Rohit Galatage | 2016-11-01 |
| 9478661 | Semiconductor device structures with self-aligned fin structure(s) and fabrication methods thereof | Ruilong Xie, Chanro Park, Min Gyu Sung | 2016-10-25 |
| 9478538 | Methods for forming transistor devices with different threshold voltages and the resulting devices | Ruilong Xie, Min Gyu Sung, Chanro Park | 2016-10-25 |
| 9461171 | Methods of increasing silicide to epi contact areas and the resulting devices | Ruilong Xie, Naim Moumen, Chanro Park, William J. Taylor, Jr. | 2016-10-04 |
| 9425106 | Methods of performing fin cut etch processes for taper FinFET semiconductor devices and the resulting devices | Ruilong Xie, Min Gyu Sung, Chanro Park | 2016-08-23 |
| 9395620 | Pellicle | — | 2016-07-19 |
| 9391174 | Method of uniform fin recessing using isotropic etch | Min Gyu Sung, Ruilong Xie, Chanro Park | 2016-07-12 |
| 9379017 | Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark | Min Gyu Sung, Chanro Park, Ruilong Xie | 2016-06-28 |
| 9373542 | Integrated circuits and methods for fabricating integrated circuits with improved contact structures | Xunyuan Zhang, Xiuyu Cai | 2016-06-21 |
| 9362377 | Low line resistivity and repeatable metal recess using CVD cobalt reflow | Vimal Kamineni, Min Gyu Sung, Chanro Park | 2016-06-07 |