Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10438931 | Package structure and manufacturing method thereof | Han-Wen Lin, Shang-Yu Chang Chien, Nan-Chun Lin | 2019-10-08 |
| 10424526 | Chip package structure and manufacturing method thereof | Chi-An Wang, Wen-Hsiung Chang | 2019-09-24 |
| 10381278 | Testing method of packaging process and packaging structure | Shang-Yu Chang Chien, Nan-Chun Lin | 2019-08-13 |
| 10354978 | Stacked package including exterior conductive element and a manufacturing method of the same | Ming-Chih Chen, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu | 2019-07-16 |
| 10332844 | Manufacturing method of package structure | Nan-Chun Lin | 2019-06-25 |
| 10300441 | Injection mixer | — | 2019-05-28 |
| 10276526 | Semiconductor package structure and manufacturing method thereof | Nan-Chun Lin, Shang-Yu Chang Chien | 2019-04-30 |
| 10276553 | Chip package structure and manufacturing method thereof | Chi-An Wang | 2019-04-30 |
| 10269671 | Package structure and manufacturing method thereof | Nan-Chun Lin | 2019-04-23 |
| 10249585 | Stackable semiconductor package and manufacturing method thereof | Yun-Hsin Yeh | 2019-04-02 |
| 10224254 | Package process method including disposing a die within a recess of a one-piece material | Ming-Chih Chen, Hsien-Wen Hsu, Yuan-Fu Lan | 2019-03-05 |
| 10177060 | Chip package structure and manufacturing method thereof | Chi-An Wang | 2019-01-08 |
| 10177011 | Chip packaging method by using a temporary carrier for flattening a multi-layer structure | Nan-Chun Lin, Shang-Yu Chang Chien | 2019-01-08 |
| 10170458 | Manufacturing method of package-on-package structure | Chi-An Wang | 2019-01-01 |
| 10163834 | Chip package structure comprising encapsulant having concave surface | Li-Chih Fang, Nan-Chun Lin, Shang-Yu Chang Chien | 2018-12-25 |
| 10157828 | Chip package structure with conductive pillar and a manufacturing method thereof | Nan-Chun Lin | 2018-12-18 |
| 10141276 | Semiconductor package structure and manufacturing method thereof | Nan-Chun Lin, Shang-Yu Chang Chien | 2018-11-27 |
| 10079218 | Test method for a redistribution layer | Han-Wen Lin, Shang-Yu Chang-Chien, Nan-Chun Lin | 2018-09-18 |
| 10002848 | Test method for a redistribution layer | Han-Wen Lin, Shang-Yu Chang-Chien, Nan-Chun Lin | 2018-06-19 |
| 9991206 | Package method including forming electrical paths through a mold layer | LIEN CHIA CHANG, Chih-Ming Ko | 2018-06-05 |
| 9972554 | Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof | Li-Chih Fang, Chia-Chang Chang, Wen-Hsiung Chang, KEE-WEI CHUNG, Chia-Wen Lien | 2018-05-15 |
| 9825005 | Semiconductor package with Pillar-Top-Interconnection (PTI) configuration and its MIS fabricating method | Yun-Hsin Yeh | 2017-11-21 |
| 8237273 | Metal post chip connecting device and method free to use soldering material | Chih-Ming Ko | 2012-08-07 |
| 8212349 | Semiconductor package having chip using copper process | Chin-Ming Hsu, Jui-Ching Hsu | 2012-07-03 |
| 8115319 | Flip chip package maintaining alignment during soldering | Chih-Ming Ko | 2012-02-14 |