Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of forming low resistance and reliable via in inter-level dielectric interconnect

Method of forming low resistance and reliable via in inter-level dielectric interconnect

US Patent 7223691 · Granted May 29, 2007

Estimated economic value: $6,985,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Reduced capacitance between power via bar and gates2025
Backside self aligned skip via2025
Airgap spacer for power via2025
Semiconductor passive device integration for silicon-on-insulator substrate2025
Early backside first power delivery network2025
Source/drain contact at tight cell boundary2025
BEOL interconnect subtractive etch super via2025
Interconnect structures with vias having vertical and horizontal sections2025
Wrap around metal via structure2025
Metal hard mask integration for active device structures2025
Vertical transport field effect transistor (VTFET) with backside wraparound cont2025
MRAM integration with self-aligned direct back side contact2025