Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

US Patent 7191373 · Granted Mar 13, 2007

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor structure with a gate and a shielding structure2025
Virtual object control method and apparatus, terminal, and storage medium2025
Incremental compilation for FPGA-based systems2025
Multi-channel static CT device2024
Transcriptome in vivo analysis (TIVA) and transcriptome in situ analysis (TISA)2024
Heterogenous voltage-based testing via on-chip voltage regulator circuits2023
Baggage cart2022
Semiconductor manufacturing apparatus including a beam shaper for shaping a lase2022
Timing-aware testing2022
Security inspection system and method2022
Golf course management tool2021
Transcriptome in vivo analysis (TIVA) and transcriptome in situ analysis (TISA)2021