Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7015092 | Methods for forming vertical gate transistors providing improved isolation and alignment of vertical gate contacts | Norbert Arnold | 2006-03-21 |
| 6995046 | Process for making byte erasable devices having elements made with nanotubes | Thomas Rueckes, Claude L. Bertin | 2006-02-07 |
| 6960818 | Recessed shallow trench isolation structure nitride liner and method for making same | Rajesh Rengarajan | 2005-11-01 |
| 6944054 | NRAM bit selectable two-device nanotube array | Thomas Rueckes, Brent M. Segal, Bernhard Vogeli, Darren K. Brock, Claude L. Bertin | 2005-09-13 |
| 6924538 | Devices having vertically-disposed nanofabric articles and methods of making the same | Jonathan W. Ward, Thomas Rueckes, Brent M. Segal | 2005-08-02 |
| 6884676 | Vertical 8F2 cell dram with active area self-aligned to bit line | Norbert Arnold | 2005-04-26 |
| 6849496 | DRAM with vertical transistor and trench capacitor memory cells and method of fabrication | Mihel Seitz, Norbert Arnold | 2005-02-01 |
| 6809368 | TTO nitride liner for improved collar protection and TTO reliability | Rama Divakaruni, Thomas W. Dyer, Rajeev Malik, Jack A. Mandelman | 2004-10-26 |
| 6768155 | Circuit with buried strap including liner | Rajiv Ranade | 2004-07-27 |
| 6621112 | DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication | Mihel Seitz, Norbert Arnold | 2003-09-16 |
| 6605504 | Method of manufacturing circuit with buried strap including a liner | Rajiv Ranade | 2003-08-12 |
| 6509226 | Process for protecting array top oxide | Jack A. Mandelman, Ramachandra Divakaruni, Rajeev Malik, Mihel Seitz | 2003-01-21 |
| 6486675 | In-situ method for measuring the endpoint of a resist recess etch process | Ulrich Mantz | 2002-11-26 |
| 6150231 | Overlay measurement technique using moire patterns | Karl Paul Muller, Christopher Gould | 2000-11-21 |
| 6124141 | Non-destructive method and device for measuring the depth of a buried interface | K. Paul Muller | 2000-09-26 |
| 5940717 | Recessed shallow trench isolation structure nitride liner and method for making same | Rajesh Rengarajan | 1999-08-17 |