Issued Patents All Time
Showing 101–125 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5894440 | Semiconductor memory device and data transferring structure and method therein | Masaki Tsukude, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi | 1999-04-13 |
| 5883427 | Semiconductor device power supply wiring structure | — | 1999-03-16 |
| 5872737 | Semiconductor integrated circuit device in which influence of power supply noise on internal circuitry during operation of input/output buffer is prevented | Takahiro Tsuruda | 1999-02-16 |
| RE36089 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai, Mikio Asakura +4 more | 1999-02-09 |
| 5870348 | Dynamic semiconductor memory device having excellent charge retention characteristics | Shigeki Tomishima | 1999-02-09 |
| 5867436 | Random access memory with a plurality amplifier groups for reading and writing in normal and test modes | Kiyohiro Furutani, Koichiro Mashiko, Noriaki Matsumoto, Yoshio Matsuda | 1999-02-02 |
| RE36027 | Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages | Kazuyasu Fujishima, Hideto Hidaka, Masaki Tsukude, Tsukasa Ohishi | 1999-01-05 |
| 5856951 | Semiconductor memory device with an improved hierarchical power supply line configuration | Masaki Tsukude | 1999-01-05 |
| 5854561 | Switched substrate bias for MOS DRAM circuits | Masaki Tsukude | 1998-12-29 |
| 5847420 | Semiconductor integrated circuit having three wiring layers | Shigehiro Kuge | 1998-12-08 |
| 5844295 | Semiconductor device having a fuse and an improved moisture resistance | Masaki Tsukude | 1998-12-01 |
| 5841172 | SOI input protection circuit | Fukashi Morishita | 1998-11-24 |
| 5838627 | Arrangement of power supply and data input/output pads in semiconductor memory device | Shigeki Tomishima, Mikio Asakura, Masaki Tsukude | 1998-11-17 |
| 5838047 | CMOS substrate biasing for threshold voltage control | Tadaaki Yamauchi | 1998-11-17 |
| 5825705 | Semiconductor memory device having self-refreshing function | Masaki Tsukude | 1998-10-20 |
| 5822264 | Dynamic semiconductor memory device with SOI structure and body refresh circuitry | Shigeki Tomishima | 1998-10-13 |
| 5815454 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Hideto Hidaka | 1998-09-29 |
| 5808949 | Semiconductor memory | — | 1998-09-15 |
| 5798976 | Semiconductor memory device with reduced current consumption in data holding mode | — | 1998-08-25 |
| 5796664 | Semiconductor memory device having divided word line | Takahiro Tsuruda | 1998-08-18 |
| 5734614 | Dynamic semiconductor memory device using sense amplifier as cache memory | Takahiro Tsuruda | 1998-03-31 |
| 5726946 | Semiconductor integrated circuit device having hierarchical power source arrangement | Tadato Yamagata, Masaki Tsukude | 1998-03-10 |
| 5726943 | Fast memory device allowing suppression of peak value of operational current | Tadato Yamagata | 1998-03-10 |
| 5724293 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Hideto Hidaka | 1998-03-03 |
| 5703522 | Switched substrate bias for MOS-DRAM circuits | Masaki Tsukude | 1997-12-30 |