Issued Patents All Time
Showing 51–75 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6418075 | Semiconductor merged logic and memory capable of preventing an increase in an abnormal current during power-up | Hiroki Shimano, Yasuhiro Ishizuka, Seizou Furubeppu, Hiroki Sugano | 2002-07-09 |
| 6418067 | Semiconductor memory device suitable for merging with logic | Naoya Watanabe, Akira Yamazaki, Takeshi Fujino, Isamu Hayashi, Hideyuki Noda | 2002-07-09 |
| 6414883 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Shigeki Tomishima +1 more | 2002-07-02 |
| 6414890 | Semiconductor memory device capable of reliably performing burn-in test at wafer level | Hiroki Shimano | 2002-07-02 |
| 6404684 | Test interface circuit and semiconductor integrated circuit device including the same | Hiroki Shimano | 2002-06-11 |
| 6404056 | Semiconductor integrated circuit | Shigehiro Kuge, Masaki Tsukude, Kazuyasu Fujishima | 2002-06-11 |
| 6400628 | Semiconductor memory device | Katsumi Dosaka, Hiroki Shimano, Hiroki Sugano | 2002-06-04 |
| 6400625 | Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester | Hiroki Shimano, Katsumi Dosaka | 2002-06-04 |
| 6388929 | Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same | Hiroki Shimano | 2002-05-14 |
| 6388329 | Semiconductor integrated circuit having three wiring layers | Shigehiro Kuge | 2002-05-14 |
| 6377508 | Dynamic semiconductor memory device having excellent charge retention characteristics | Shigeki Tomishima | 2002-04-23 |
| 6377483 | Semiconductor memory device having improved memory cell and bit line pitch | Hiroki Shimano, Toshinori Morihara | 2002-04-23 |
| 6373321 | CMOS semiconductor device | Tadaaki Yamauchi | 2002-04-16 |
| 6341098 | Semiconductor integrated circuit device having hierarchical power source arrangement | Tadato Yamagata, Masaki Tsukude | 2002-01-22 |
| 6337506 | Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area | Fukashi Morishita, Teruhiko Amano, Tetsushi Tanizaki, Takeshi Fujino, Takahiro Tsuruda +2 more | 2002-01-08 |
| 6333889 | Logic-merged semiconductor memory having high internal data transfer rate | — | 2001-12-25 |
| 6304494 | Semiconductor device with decreased power consumption | — | 2001-10-16 |
| 6272055 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Shigeki Tomishima +1 more | 2001-08-07 |
| 6272034 | Semiconductor memory device | Mitsuya Kinoshita, Fukashi Morishita, Takeshi Fujino, Tetsushi Tanizaki, Takahiro Tsuruda +2 more | 2001-08-07 |
| 6256252 | Memory-embedded semiconductor integrated circuit device having low power consumption | — | 2001-07-03 |
| 6246625 | Semiconductor integrated circuit device having hierarchical power source arrangement | Tadato Yamagata, Masaki Tsukude | 2001-06-12 |
| 6232793 | Switched backgate bias for FET | Masaki Tsukude | 2001-05-15 |
| 6215720 | High speed operable semiconductor memory device with memory blocks arranged about the center | Teruhiko Amano, Takahiro Tsuruda, Tetsushi Tanizaki, Takeshi Fujino, Mitsuya Kinoshita +2 more | 2001-04-10 |
| 6214664 | Method of manufacturing semiconductor device | Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Tadato Yamagata, Kazuyasu Fujishima | 2001-04-10 |
| 6181005 | Semiconductor device wiring structure | — | 2001-01-30 |