Issued Patents All Time
Showing 151–175 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5325336 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Hideto Hidaka | 1994-06-28 |
| 5321657 | Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages | Kazuyasu Fujishima, Hideto Hidaka, Masaki Tsukude, Tsukasa Ohishi | 1994-06-14 |
| 5321646 | Layout of a semiconductor memory device | Shigeki Tomishima, Mikio Asakura, Hideto Hidaka, Masanori Hayashikoshi | 1994-06-14 |
| 5315166 | Substrate voltage generator and method therefor in a semiconductor device having selectively activated internal stepped-down power supply voltages | — | 1994-05-24 |
| 5315548 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai, Mikio Asakura +4 more | 1994-05-24 |
| 5304859 | Substrate voltage generator and method therefor in a semiconductor device having internal stepped-down power supply voltage | — | 1994-04-19 |
| 5293598 | Random access memory with a plurality of amplifier groups | Kiyohiro Furutani, Koichiro Mashiko, Noriaki Matsumoto, Yoshio Matsuda | 1994-03-08 |
| 5289417 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Masaki Tsukude, Kazuyasu Fujishima | 1994-02-22 |
| 5279984 | Method for producing a semiconductor integrated circuit device in which circuit functions can be remedied or changed | Mitsuya Kinoshita, Kiyohiro Furutani | 1994-01-18 |
| 5267214 | Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor | Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude | 1993-11-30 |
| 5249155 | Semiconductor device incorporating internal voltage down converting circuit | Hideto Hidaka, Mikio Asakura, Masanori Hayashikoshi, Masaki Tsukude, Shinji Kawai +1 more | 1993-09-28 |
| 5226009 | Semiconductor memory device supporting cache and method of driving the same | — | 1993-07-06 |
| 5223735 | Semiconductor integrated circuit device in which circuit functions can be remedied or changed and the method for producing the same | Mitsuya Kinoshita, Kiyohiro Furutani | 1993-06-29 |
| 5185744 | Semiconductor memory device with test circuit | Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude | 1993-02-09 |
| 5184327 | Semiconductor memory device having on-chip test circuit and method for testing the same | Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude, Kazuyasu Fujishima | 1993-02-02 |
| 5136543 | Data descrambling in semiconductor memory device | Yoshio Matsuda, Kazuyasu Fujishima, Masaki Tsukude, Tsukasa Oishi | 1992-08-04 |
| 5132930 | CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines | Kiyohiro Furutani, Koichiro Mashiko, Noriaki Matsumoto, Yoshio Matsuda | 1992-07-21 |
| 5088063 | Semiconductor memory device having on-chip test circuit | Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude, Kazuyasu Fujishima | 1992-02-11 |
| 5084746 | Semiconductor memory device | Koichiro Mashiko, Kiyohiro Furutani | 1992-01-28 |
| 5060230 | On chip semiconductor memory arbitrary pattern, parallel test apparatus and method | Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude | 1991-10-22 |
| 5058058 | Structure for sense amplifier arrangement in semiconductor memory device | Kenichi Yasuda | 1991-10-15 |
| 5045899 | Dynamic random access memory having stacked capacitor structure | — | 1991-09-03 |
| 5022007 | Test signal generator for semiconductor integrated circuit memory and testing method thereof | Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude, Kazuyasu Fujishima | 1991-06-04 |
| 5012472 | Dynamic type semiconductor memory device having an error checking and correcting circuit | Kiyohiro Furutani, Koichiro Mashiko | 1991-04-30 |
| 5003542 | Semiconductor memory device having error correcting circuit and method for correcting error | Koichiro Mashiko, Kiyohiro Furutani | 1991-03-26 |