Issued Patents All Time
Showing 126–150 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5696727 | Semiconductor memory device provided with sense amplifier capable of high speed operation with low power consumption | Masaki Tsukude, Shigeki Tomishima | 1997-12-09 |
| 5694364 | Semiconductor integrated circuit device having a test mode for reliability evaluation | Fukashi Morishita, Masaki Tsukude | 1997-12-02 |
| 5687123 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Shigeki Tomishima +1 more | 1997-11-11 |
| 5666315 | Semiconductor memory device having a redundancy function suppressible of leakage current from a defective memory cell | Masaki Tsukude | 1997-09-09 |
| 5659517 | Semiconductor memory device with an improved hierarchical power supply line configuration | Masaki Tsukude | 1997-08-19 |
| 5657286 | Semiconductor memory device having improved manner of data line connection in hierarchical data line structure | — | 1997-08-12 |
| 5650972 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Hideto Hidaka | 1997-07-22 |
| 5646900 | Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device | Masaki Tsukude | 1997-07-08 |
| 5636163 | Random access memory with a plurality amplifier groups for reading and writing in normal and test modes | Kiyohiro Furutani, Koichiro Mashiko, Noriaki Matsumoto, Yoshio Matsuda | 1997-06-03 |
| 5633831 | Semiconductor memory device having self-refreshing function | Masaki Tsukude | 1997-05-27 |
| 5631870 | Semiconductor memory | — | 1997-05-20 |
| 5617369 | Dynamic semiconductor memory device having excellent charge retention characteristics | Shigeki Tomishima | 1997-04-01 |
| 5612919 | Method of testing an operation of a semiconductor memory device and semiconductor memory device which can be subjected to such an operation test | — | 1997-03-18 |
| 5610533 | Switched substrate bias for logic circuits | Masaki Tsukude | 1997-03-11 |
| 5604707 | Semiconductor memory device responsive to hierarchical internal potentials | Shigehiro Kuge, Shigeki Tomishima, Hideto Hidaka, Takahiro Tsuruda | 1997-02-18 |
| 5604710 | Arrangement of power supply and data input/output pads in semiconductor memory device | Shigeki Tomishima, Mikio Asakura, Masaki Tsukude | 1997-02-18 |
| 5602793 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Hideto Hidaka | 1997-02-11 |
| 5568440 | Semiconductor memory device having self-refreshing function | Masaki Tsukude | 1996-10-22 |
| 5537073 | Circuitry and method for clamping a boost signal | — | 1996-07-16 |
| 5519657 | Semiconductor memory device having a redundant memory array and a testing method thereof | — | 1996-05-21 |
| 5513142 | Semiconductor memory device for maintaining level of signal line | Shigeki Tomishima, Hideto Hidaka | 1996-04-30 |
| 5510749 | Circuitry and method for clamping a boost signal | — | 1996-04-23 |
| 5504713 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Masaki Tsukude, Kazuyasu Fujishima | 1996-04-02 |
| 5426615 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Hideto Hidaka | 1995-06-20 |
| 5375088 | Random access memory with plurality of amplifier groups | Kiyohiro Furutani, Koichiro Mashiko, Noriaki Matsumoto, Yoshio Matsuda | 1994-12-20 |