Issued Patents All Time
Showing 51–75 of 139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7227261 | Vertical surface mount assembly and methods | Larry D. Kinsman, Jerry M. Brooks, Warren M. Farnworth, Walter L. Moden | 2007-06-05 |
| 7168027 | Dynamic synchronization of data capture on an optical or other high speed communications link | Joseph M. Jeddeloh | 2007-01-23 |
| 7120727 | Reconfigurable memory module and method | Joseph M. Jeddeloh | 2006-10-10 |
| 7106611 | Wavelength division multiplexed memory module, memory system and method | Joseph M. Jeddeloh | 2006-09-12 |
| 7107415 | Posted write buffers and methods of posting write requests in memory modules | Joseph M. Jeddeloh | 2006-09-12 |
| 7102907 | Wavelength division multiplexed memory module, memory system and method | Joseph M. Jeddeloh | 2006-09-05 |
| 7076697 | Method and apparatus for monitoring component latency drifts | — | 2006-07-11 |
| 7065868 | Methods for installing a circuit device | Larry D. Kinsman, Mike Brooks, Warren M. Farnworth, Walter L. Moden | 2006-06-27 |
| 6982892 | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules | Joseph M. Jeddeloh | 2006-01-03 |
| 6963941 | High speed bus topology for expandable systems | — | 2005-11-08 |
| 6961259 | Apparatus and methods for optically-coupled memory systems | Kevin J. Ryan | 2005-11-01 |
| 6934785 | High speed interface with looped bus | Roy Greeff, David K. Ovard | 2005-08-23 |
| 6928019 | Semiconductor device with self refresh test mode | — | 2005-08-09 |
| 6898726 | Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations | — | 2005-05-24 |
| 6889357 | Timing calibration pattern for SLDRAM | Brent Keeth, Brian Johnson, Paul Fuller | 2005-05-03 |
| 6871253 | Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection | Roy Greeff, David K. Ovard | 2005-03-22 |
| 6856567 | Semiconductor device with self refresh test mode | — | 2005-02-15 |
| 6845460 | Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register | Kevin J. Ryan, Joseph M. Jeddeloh | 2005-01-18 |
| 6837731 | Locking assembly for securing a semiconductor device to a carrier substrate | David J. Corisis, Jerry M. Brooks | 2005-01-04 |
| 6820181 | Method and system for controlling memory accesses to memory modules having a memory hub architecture | Joseph M. Jeddeloh | 2004-11-16 |
| 6816426 | Semiconductor device with self refresh test mode | — | 2004-11-09 |
| 6792372 | Method and apparatus for independent output driver calibration | — | 2004-09-14 |
| 6789175 | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths | Kevin J. Ryan | 2004-09-07 |
| 6784367 | Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies | Ernest J. Russell, Bharath Nagabhushanam, Roger D. Norwood | 2004-08-31 |
| 6747344 | Lead frame assemblies with voltage reference plane and IC packages including same | David J. Corisis, Jerry M. Brooks | 2004-06-08 |