Issued Patents All Time
Showing 26–50 of 139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7911819 | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules | Joseph M. Jeddeloh | 2011-03-22 |
| 7908452 | Method and system for controlling memory accesses to memory modules having a memory hub architecture | Joseph M. Jeddeloh | 2011-03-15 |
| 7894192 | Integrated circuit package support system | David J. Corisis, Walter L. Moden | 2011-02-22 |
| 7871859 | Vertical surface mount assembly and methods | Larry D. Kinsman, Jerry M. Brooks, Warren M. Farnworth, Walter L. Moden | 2011-01-18 |
| 7818712 | Reconfigurable memory module and method | Joseph M. Jeddeloh | 2010-10-19 |
| 7721135 | Method of timing calibration using slower data rate pattern | Kevin J. Ryan, Joseph M. Jeddeloh | 2010-05-18 |
| 7716444 | Method and system for controlling memory accesses to memory modules having a memory hub architecture | Joseph M. Jeddeloh | 2010-05-11 |
| 7613026 | Apparatus and methods for optically-coupled memory systems | Kevin J. Ryan | 2009-11-03 |
| 7600314 | Methods for installing a plurality of circuit devices | Larry D. Kinsman, Mike Brooks, Warren M. Farnworth, Walter L. Moden | 2009-10-13 |
| 7529896 | Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules | Joseph M. Jeddeloh | 2009-05-05 |
| 7461188 | Capacitive multidrop bus compensation | Roy Greeff | 2008-12-02 |
| 7437579 | System and method for selective memory module power management | Joseph M. Jeddeloh | 2008-10-14 |
| 7428644 | System and method for selective memory module power management | Joseph M. Jeddeloh | 2008-09-23 |
| 7428181 | Semiconductor device with self refresh test mode | — | 2008-09-23 |
| 7414875 | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules | Joseph M. Jeddeloh | 2008-08-19 |
| 7412566 | Memory hub and access method having internal prefetch buffers | Joseph M. Jeddeloh | 2008-08-12 |
| 7379315 | Apparatus and methods for optically-coupled memory systems | Kevin J. Ryan | 2008-05-27 |
| 7376857 | Method of timing calibration using slower data rate pattern | Kevin J. Ryan, Joseph M. Jeddeloh | 2008-05-20 |
| 7352603 | Apparatus and methods for optically-coupled memory systems | Kevin J. Ryan | 2008-04-01 |
| 7343444 | Reconfigurable memory module and method | Joseph M. Jeddeloh | 2008-03-11 |
| 7287108 | Capacitive multidrop bus compensation | Roy Greeff | 2007-10-23 |
| 7280382 | Apparatus and methods for optically-coupled memory systems | Kevin J. Ryan | 2007-10-09 |
| 7280381 | Apparatus and methods for optically-coupled memory systems | Kevin J. Ryan | 2007-10-09 |
| 7260685 | Memory hub and access method having internal prefetch buffers | Joseph M. Jeddeloh | 2007-08-21 |
| 7249236 | Method and system for controlling memory accesses to memory modules having a memory hub architecture | Joseph M. Jeddeloh | 2007-07-24 |