Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11009548 | Testing fuse configurations in semiconductor devices | Adrian E. Ong, Paul Fuller, Nick van Heel | 2021-05-18 |
| 10302696 | Testing fuse configurations in semiconductor devices | Adrian E. Ong, Paul Fuller, Nick van Heel | 2019-05-28 |
| 9568544 | Testing fuse configurations in semiconductor devices | Adrian E. Ong, Paul Fuller, Nick van Heel | 2017-02-14 |
| 8717052 | Testing fuse configurations in semiconductor devices | Adrian E. Ong, Paul Fuller, Nick van Heel | 2014-05-06 |
| 8063650 | Testing fuse configurations in semiconductor devices | Adrian E. Ong, Paul Fuller, Nick van Heel | 2011-11-22 |
| 7562268 | Method and apparatus for testing a memory device with compressed data using a single output | Mirmajid Seyyedy | 2009-07-14 |
| 7251715 | Double data rate scheme for data output | Wen Li | 2007-07-31 |
| 7093095 | Double data rate scheme for data output | Wen Li | 2006-08-15 |
| 6976195 | Method and apparatus for testing a memory device with compressed data using a single output | Mirmajid Seyyedy | 2005-12-13 |
| 6954388 | Delay locked loop control circuit | Wen Li | 2005-10-11 |
| 6901013 | Controller for delay locked loop circuits | William F. Jones, Wen Li, Timothy B. Cowles, Daniel R. Loughmiller | 2005-05-31 |
| 6836437 | Method of reducing standby current during power down mode | Wen Li, Daniel R. Loughmiller, Scott E. Schaefer | 2004-12-28 |
| 6809974 | Controller for delay locked loop circuits | William F. Jones, Wen Li, Timothy B. Cowles, Daniel R. Loughmiller | 2004-10-26 |
| 6809990 | Delay locked loop control circuit | Wen Li | 2004-10-26 |
| 6763444 | Read/write timing calibration of a memory array using a row or a redundant row | Christopher K. Morzano, Wen Li | 2004-07-13 |
| 6694416 | Double data rate scheme for data output | Wen Li | 2004-02-17 |
| 6665219 | Method of reducing standby current during power down mode | Wen Li, Daniel R. Loughmiller, Scott E. Schaefer | 2003-12-16 |
| 6487207 | Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology | — | 2002-11-26 |
| 6438060 | Method of reducing standby current during power down mode | Wen Li, Daniel R. Loughmiller, Scott E. Schaefer | 2002-08-20 |
| 6392453 | Differential input buffer bias circuit | Christopher K. Morzano | 2002-05-21 |
| 6330194 | High speed I/O calibration using an input path and simplified logic | Terry R. Lee | 2001-12-11 |
| 6201751 | Integrated circuit power-up controllers, integrated circuit power-up circuits, and integrated circuit power-up methods | — | 2001-03-13 |
| 6081528 | Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology | — | 2000-06-27 |
| 5964896 | Method and apparatus for a high speed cyclical redundancy check system | Huy T. Vo, Charles L. Ingalls | 1999-10-12 |
| 5953258 | Data transfer in a memory device having complete row redundancy | — | 1999-09-14 |