Issued Patents All Time
Showing 25 most recent of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12158826 | Storing memory array operational information in non-volatile subarrays | Christopher John Kawamura, Scott J. Derner | 2024-12-03 |
| 12114474 | Integrated memory comprising secondary access devices between digit lines and primary access devices | Scott J. Derner | 2024-10-08 |
| 12022663 | Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors | Scott J. Derner | 2024-06-25 |
| 11967362 | Pre-sense gut node amplification in sense amplifier | Huy T. Vo, Christopher K. Morzano, Christopher John Kawamura | 2024-04-23 |
| 11715513 | Apparatuses and methods for sense line architectures for semiconductor memories | Toby D. Robbs | 2023-08-01 |
| 11699473 | FX driver circuit | Tae H. Kim | 2023-07-11 |
| 11636890 | Array data bit inversion | Scott J. Derner | 2023-04-25 |
| 11450668 | Integrated memory comprising secondary access devices between digit lines and primary access devices | Scott J. Derner | 2022-09-20 |
| 11450740 | Integrated memory comprising gated regions between charge-storage devices and access devices | Scott J. Derner | 2022-09-20 |
| 11392468 | Storing memory array operational information in non-volatile subarrays | Christopher John Kawamura, Scott J. Derner | 2022-07-19 |
| 11380388 | Memory arrays with vertical thin film transistors coupled between digit lines | Scott J. Derner | 2022-07-05 |
| 11342014 | Driver leakage control | — | 2022-05-24 |
| 11264394 | Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors | Scott J. Derner | 2022-03-01 |
| 11250900 | Half density ferroelectric memory and operation | Scott J. Derner | 2022-02-15 |
| 11232829 | Apparatuses and methods for sense line architectures for semiconductor memories | Toby D. Robbs | 2022-01-25 |
| 11232828 | Integrated memory assemblies comprising multiple memory array decks | Scott J. Derner | 2022-01-25 |
| 11227861 | Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array | Hiroki Fujisawa, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner | 2022-01-18 |
| 11200937 | Reprogrammable non-volatile ferroelectric latch for use with a memory controller | Scott J. Derner, Christopher John Kawamura | 2021-12-14 |
| 11176987 | Dram array architecture with row hammer stress mitigation | Christopher John Kawamura, Tae H. Kim | 2021-11-16 |
| 11062753 | Array data bit inversion | Scott J. Derner | 2021-07-13 |
| 11031400 | Integrated memory comprising secondary access devices between digit lines and primary access devices | Scott J. Derner | 2021-06-08 |
| 10998027 | Memory circuitry | Scott J. Derner, Tae H. Kim | 2021-05-04 |
| 10957681 | Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array | Hiroki Fujisawa, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner | 2021-03-23 |
| 10957382 | Integrated assemblies comprising vertically-stacked memory array decks and folded digit line connections | Scott J. Derner | 2021-03-23 |
| 10943642 | Integrated memory assemblies comprising multiple memory array decks | Scott J. Derner | 2021-03-09 |