Issued Patents All Time
Showing 25 most recent of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400730 | Semiconductor device having memory cell array divided into plural memory mats | Susumu Takahashi | 2025-08-26 |
| 12132201 | Negative electrode and method for producing negative electrode, and electrode binding agent | Takeshi Kondo, Tomokuni ABE, Keigo OYAIZU, Tomoyuki TASAKI | 2024-10-29 |
| 11705432 | Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices | Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa | 2023-07-18 |
| 11646092 | Shared error check and correct logic for multiple data banks | Susumu Takahashi | 2023-05-09 |
| 11227861 | Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array | Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner | 2022-01-18 |
| 11207354 | Schwann cell differentiation promoting agent and a peripheral nerve regeneration promoting agent | Hiroyuki Tanaka, Tsuyoshi Murase, Hideki Yoshikawa | 2021-12-28 |
| 11081468 | Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses | Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa | 2021-08-03 |
| 10957681 | Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array | Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner | 2021-03-23 |
| 10957413 | Shared error check and correct logic for multiple data banks | Susumu Takahashi | 2021-03-23 |
| 10755758 | Methods and apparatuses including command delay adjustment circuit | Shuichi Ishibashi, Kazutaka Miyano | 2020-08-25 |
| 10290336 | Methods and apparatuses including command delay adjustment circuit | Shuichi Ishibashi, Kazutaka Miyano | 2019-05-14 |
| 10210922 | Apparatus and methods for refreshing memory cells of a semiconductor device | Kenji Yoshida | 2019-02-19 |
| 10004716 | Therapeutic/ preventive agent containing coumarin derivative as active ingredient | Mitsuru Naiki, Takumi Numazawa | 2018-06-26 |
| 9984738 | Apparatuses and methods for refreshing memory cells of a semiconductor device | Kenji Yoshida | 2018-05-29 |
| 9978438 | Device having multiple switching buffers for data paths controlled based on IO configuration modes | — | 2018-05-22 |
| 9892780 | Semiconductor memory device including output buffer | Hiromasa Takeda | 2018-02-13 |
| 9881665 | Semiconductor memory device including output buffer | Hiromasa Takeda | 2018-01-30 |
| 9865317 | Methods and apparatuses including command delay adjustment circuit | Shuichi Ishibashi, Kazutaka Miyano | 2018-01-09 |
| 9786352 | Semiconductor memory device including refresh operations having first and second cycles | Kenji Yoshida | 2017-10-10 |
| 9704561 | Device having multiple switching buffers for data paths controlled based on IO configuration modes | — | 2017-07-11 |
| 9641175 | Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit | — | 2017-05-02 |
| 9627013 | Semiconductor memory device including output buffer | Hiromasa Takeda | 2017-04-18 |
| 9570119 | Information processing system including semiconductor device having self-refresh mode | — | 2017-02-14 |
| 9570122 | Device having multiple switching buffers for data paths controlled based on IO configuration modes | — | 2017-02-14 |
| 9530459 | Semiconductor memory device including a repeater circuit on main data lines | Shingo Mitsubori | 2016-12-27 |