Issued Patents All Time
Showing 26–50 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10930653 | Apparatuses comprising memory cells, and apparatuses comprising memory arrays | Scott J. Derner, Michael A. Shore, Steve V. Cole | 2021-02-23 |
| 10916295 | Memory arrays with vertical thin film transistors coupled between digit lines | Scott J. Derner | 2021-02-09 |
| 10916548 | Memory arrays with vertical access transistors | Scott J. Derner | 2021-02-09 |
| 10910038 | DRAM array architecture with row hammer stress mitigation | Christopher John Kawamura, Tae H. Kim | 2021-02-02 |
| 10910049 | Sub-word line driver circuit | Tae H. Kim | 2021-02-02 |
| 10896722 | Integrated assemblies having sense-amplifier-circuitry distributed amongst two or more locations, and having circuitry configured to isolate local column-select-structures from a global structure | Jiyun Li | 2021-01-19 |
| 10896706 | FX driver circuit | Tae H. Kim | 2021-01-19 |
| 10872648 | Apparatuses and methods for reducing row address to column address delay | — | 2020-12-22 |
| 10854617 | Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors | Scott J. Derner | 2020-12-01 |
| 10811083 | Integrated assemblies comprising supplemental sense-amplifier-circuitry for refresh | Scott J. Derner | 2020-10-20 |
| 10796743 | Dynamic adjustment of memory cell digit line capacitance | Christopher John Kawamura, Scott J. Derner | 2020-10-06 |
| 10783949 | Half density ferroelectric memory and operation | Scott J. Derner | 2020-09-22 |
| 10748596 | Array data bit inversion | Scott J. Derner | 2020-08-18 |
| 10726907 | Electronic device with a sense amp mechanism | Scott J. Derner | 2020-07-28 |
| 10672456 | Three dimensional memory devices | Fredrick Fishburn | 2020-06-02 |
| 10672435 | Sense amplifier signal boost | Christopher John Kawamura | 2020-06-02 |
| 10658024 | Systems and methods for dynamic random access memory (DRAM) cell voltage boosting | Scott J. Derner, Tae H. Kim | 2020-05-19 |
| 10622057 | Tri-level DRAM sense amplifer | Christopher John Kawamura, Scott J. Derner | 2020-04-14 |
| 10614874 | Integrated memory assemblies comprising multiple memory array decks | Scott J. Derner | 2020-04-07 |
| 10607687 | Apparatuses and methods for sense line architectures for semiconductor memories | Toby D. Robbs | 2020-03-31 |
| 10580464 | Sense amplifier constructions | Scott J. Derner | 2020-03-03 |
| 10535388 | Apparatuses and methods for reducing row address to column address delay | — | 2020-01-14 |
| 10510394 | Reprogrammable non-volatile ferroelectric latch for use with a memory controller | Scott J. Derner, Christopher John Kawamura | 2019-12-17 |
| 10431282 | Array data bit inversion | Scott J. Derner | 2019-10-01 |
| 10431284 | Dynamic reference voltage determination | Scott J. Derner, Christopher John Kawamura | 2019-10-01 |