Issued Patents All Time
Showing 25 most recent of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367919 | Word line driver circuitry including shared driver gates, and associated methods, devices, and systems | J. Wayne Thompson, Brenton P. Van Leeuwen | 2025-07-22 |
| 12158826 | Storing memory array operational information in non-volatile subarrays | Scott J. Derner, Charles L. Ingalls | 2024-12-03 |
| 12106820 | Single column select architecture for sense amplifier circuity | Luoqi Li, Huy T. Vo | 2024-10-01 |
| 12080336 | Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors | Jiyun Li, Tae H. Kim | 2024-09-03 |
| 12051460 | Apparatuses and methods for single-ended sense amplifiers | Tae H. Kim, Jiyun Li | 2024-07-30 |
| 11967362 | Pre-sense gut node amplification in sense amplifier | Huy T. Vo, Christopher K. Morzano, Charles L. Ingalls | 2024-04-23 |
| 11948622 | Generating access line voltages | Martin Brox, C. Omar Benitez, Johnathan L. Gossi | 2024-04-02 |
| 11848042 | Multi-level storage in ferroelectric memory | — | 2023-12-19 |
| 11706909 | Integrated assemblies comprising memory cells and shielding material between the memory cells | Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Hiroaki Taketani | 2023-07-18 |
| 11574668 | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory | Scott J. Derner | 2023-02-07 |
| 11475934 | Ferroelectric memory cell sensing | Scott J. Derner | 2022-10-18 |
| 11443780 | Vertical access line multiplexor | Yuan He, Beau D. Barry, Tae H. Kim | 2022-09-13 |
| 11392468 | Storing memory array operational information in non-volatile subarrays | Scott J. Derner, Charles L. Ingalls | 2022-07-19 |
| 11238913 | Cell-based reference voltage generation | Scott J. Derner | 2022-02-01 |
| 11211113 | Integrated assemblies comprising wordlines having ends selectively shunted to low voltage for speed transitioning | Scott J. Derner | 2021-12-28 |
| 11205468 | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory | Scott J. Derner | 2021-12-21 |
| 11200937 | Reprogrammable non-volatile ferroelectric latch for use with a memory controller | Scott J. Derner, Charles L. Ingalls | 2021-12-14 |
| 11176987 | Dram array architecture with row hammer stress mitigation | Charles L. Ingalls, Tae H. Kim | 2021-11-16 |
| 11176978 | Apparatuses and method for reducing row address to column address delay | — | 2021-11-16 |
| 11127450 | Pre-writing memory cells of an array | Scott J. Derner | 2021-09-21 |
| 11120847 | Apparatuses and method for reducing row address to column address delay for a voltage threshold compensation sense amplifier | Tae H. Kim | 2021-09-14 |
| 11107515 | Ferroelectric memory cells | Scott J. Derner | 2021-08-31 |
| 11074964 | Integrated assemblies comprising digit lines configured to have shunted ends during a precharge operation | Jiyun Li | 2021-07-27 |
| 11056165 | Cell-specific reference generation and sensing | Scott J. Derner | 2021-07-06 |
| 11017832 | Multi-level storage in ferroelectric memory | — | 2021-05-25 |