Issued Patents All Time
Showing 25 most recent of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11967362 | Pre-sense gut node amplification in sense amplifier | Huy T. Vo, Christopher John Kawamura, Charles L. Ingalls | 2024-04-23 |
| 11015547 | Apparatuses and methods for storing redundancy repair information for memories | — | 2021-05-25 |
| 10867692 | Apparatuses and methods for latching redundancy repair addresses at a memory | Sujeet Ayyapureddi | 2020-12-15 |
| 10443531 | Apparatuses and methods for storing redundancy repair information for memories | — | 2019-10-15 |
| 10381103 | Apparatuses and methods for latching redundancy repair addresses to avoid address bits overwritten at a repair block | Sujeet Ayyapureddi | 2019-08-13 |
| 9484326 | Apparatuses having stacked devices and methods of connecting dice stacks | Brent Keeth | 2016-11-01 |
| 9123552 | Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same | Brent Keeth | 2015-09-01 |
| 8687459 | Synchronous command-based write recovery time auto-precharge control | Victor Wong, Alan J. Wilson | 2014-04-01 |
| 7944773 | Synchronous command-based write recovery time auto-precharge control | Victor Wong, Alan J. Wilson | 2011-05-17 |
| 7936181 | Method and circuit for off chip driver control, and memory device using same | Greg A. Blodgett | 2011-05-03 |
| 7764206 | Parallel-to-serial data sort device | Wen Li | 2010-07-27 |
| 7561477 | Data strobe synchronization circuit and method for double data rate, multi-bit writes | Wen Li | 2009-07-14 |
| 7525458 | Method and apparatus for converting parallel data to serial data in high speed applications | Wen Li | 2009-04-28 |
| 7463052 | Method and circuit for off chip driver control, and memory device using same | Greg A. Blodgett | 2008-12-09 |
| 7379377 | Memory array decoder | Jeffrey P. Wright | 2008-05-27 |
| 7362619 | Data strobe synchronization circuit and method for double data rate, multi-bit writes | Wen Li | 2008-04-22 |
| 7358872 | Method and apparatus for converting parallel data to serial data in high speed applications | Wen Li | 2008-04-15 |
| 7330393 | Memory array decoder | Jeffrey P. Wright | 2008-02-12 |
| 7318167 | DDR II write data capture calibration | Wen Li | 2008-01-08 |
| 7280410 | System and method for mode register control of data bus operating mode and impedance | Jeffrey W. Janzen | 2007-10-09 |
| 7245550 | Memory array decoder | Jeffrey P. Wright | 2007-07-17 |
| 7227812 | Write address synchronization useful for a DDR prefetch SDRAM | Wen Li | 2007-06-05 |
| 7215579 | System and method for mode register control of data bus operating mode and impedance | Jeffrey W. Janzen | 2007-05-08 |
| 7165185 | DDR II write data capture calibration | Wen Li | 2007-01-16 |
| 7142543 | High speed programmable counter | — | 2006-11-28 |