Issued Patents All Time
Showing 176–200 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7054198 | Flash memory with fast boot block access | Allahyar Vahidimowlavi | 2006-05-30 |
| 7054183 | Adaptive programming technique for a re-writable conductive memory device | Darrell Rinerson | 2006-05-30 |
| 7042778 | Flash array implementation with local and global bit lines | — | 2006-05-09 |
| 7042035 | Memory array with high temperature wiring | Darrell Rinerson, Steven W. Longcor, Steve Kuo-Ren Hsia, Wayne Kinney, Edmond R. Ward | 2006-05-09 |
| 7038935 | 2-terminal trapped charge memory device with voltage switchable multi-level resistance | Darrell Rinerson, Wayne Kinney, Steven W. Longcor, Edmond R. Ward, Steve Kuo-Ren Hsia | 2006-05-02 |
| 7032199 | Design rule checking integrated circuits | Adriana Ababei | 2006-04-18 |
| 7024643 | Identifying line width errors in integrated circuit designs | Adriana Ababei | 2006-04-04 |
| 7020012 | Cross point array using distinct voltages | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward | 2006-03-28 |
| 7020006 | Discharge of conductive array lines in fast memory | Darrell Rinerson | 2006-03-28 |
| 7009909 | Line drivers that use minimal metal layers | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward | 2006-03-07 |
| 7009235 | Conductive memory stack with non-uniform width | Darrell Rinerson, Steven W. Longcor | 2006-03-07 |
| 6999363 | Non-volatile memory with test rows for disturb detection | — | 2006-02-14 |
| 6982920 | Flash array implementation with local and global bit lines | — | 2006-01-03 |
| 6977854 | Flash array implementation with local and global bit lines | — | 2005-12-20 |
| 6977853 | Flash array implementation with local and global bit lines | — | 2005-12-20 |
| 6972985 | Memory element having islands | Darrell Rinerson, Philip Swab, Steve Kuo-Ren Hsia, John Sanchez, Steven W. Longcor | 2005-12-06 |
| 6973005 | Flash array implementation with local and global bit lines | — | 2005-12-06 |
| 6970375 | Providing a reference voltage to a cross point memory array | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Wayne Kinney, Steve Kuo-Ren Hsia | 2005-11-29 |
| 6961805 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure | Vinod Lakhani, Mathew L. Adsitt | 2005-11-01 |
| 6954400 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Vinod Lakhani, Mathew L. Adsitt | 2005-10-11 |
| 6948041 | Permanent memory block protection in a flash memory device | See Kit Leong | 2005-09-20 |
| 6944839 | Checking layout accuracy in integrated circuit designs | Adriana Ababei | 2005-09-13 |
| 6944812 | Mode entry circuit and method | — | 2005-09-13 |
| 6940780 | Flash array implementation with local and global bit lines | — | 2005-09-06 |
| 6940744 | Adaptive programming technique for a re-writable conductive memory device | Darrell Rinerson | 2005-09-06 |