Issued Patents All Time
Showing 201–225 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6937519 | Flash memory with fast boot block access | Allahyar Vahidimowlavi | 2005-08-30 |
| 6934207 | Flash array implementation with local and global bit lines | — | 2005-08-23 |
| 6914813 | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry | Vinod Lakhani | 2005-07-05 |
| 6909636 | Flash array implementation with local and global bit lines | — | 2005-06-21 |
| 6909632 | Multiple modes of operation in a cross point array | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Wayne Kinney, Steve Kuo-Ren Hsia | 2005-06-21 |
| 6906939 | Re-writable memory with multiple memory layers | Darrell Rinerson, Steven W. Longcor, Wayne Kinney, Edmond R. Ward | 2005-06-14 |
| 6900625 | Voltage converter system and method having a stable output voltage | Dumitru Cioaca | 2005-05-31 |
| 6879340 | CMOS imager with integrated non-volatile memory | — | 2005-04-12 |
| 6870755 | Re-writable memory with non-linear memory element | Darrell Rinerson, Steven W. Longcor, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia | 2005-03-22 |
| 6862243 | Flash array implementation with local and global bit lines | — | 2005-03-01 |
| 6859382 | Memory array of a non-volatile ram | Darrell Rinerson | 2005-02-22 |
| 6856536 | Non-volatile memory with a single transistor and resistive memory element | Darrell Rinerson | 2005-02-15 |
| 6856571 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Vinod Lakhani, Mathew L. Adsitt | 2005-02-15 |
| 6853598 | Non-volatile memory with test rows for disturb detection | — | 2005-02-08 |
| 6850429 | Cross point memory array with memory plugs exhibiting a characteristic hysteresis | Darrell Rinerson, Steven W. Longcor, Steve Kuo-Ren Hsia, Wayne Kinney, Edmond R. Ward | 2005-02-01 |
| 6850455 | Multiplexor having a reference voltage on unselected lines | Darrell Rinerson | 2005-02-01 |
| 6847552 | Flash array implementation with local and global bit lines | — | 2005-01-25 |
| 6845053 | Power throughput adjustment in flash memory | — | 2005-01-18 |
| 6842385 | Automatic reference voltage regulation in a memory device | Dumitru Cioaca, Al Vahidimowlavi, Frankie F. Roohparvar | 2005-01-11 |
| 6836421 | Line drivers that fit within a specified line pitch | Darrell Rinerson | 2004-12-28 |
| 6834008 | Cross point memory array using multiple modes of operation | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Wayne Kinney, Steve Kuo-Ren Hsia | 2004-12-21 |
| 6831854 | Cross point memory array using distinct voltages | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Wayne Kinney, Steve Kuo-Ren Hsia | 2004-12-14 |
| 6813183 | Externally triggered leakage detection and repair in a flash memory device | — | 2004-11-02 |
| 6809987 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Vinod Lakhani, Mathew L. Adsitt | 2004-10-26 |
| 6798685 | Multi-output multiplexor | Darrell Rinerson, Steven W. Longcor, Steve Kuo-Ren Hsia | 2004-09-28 |