Issued Patents All Time
Showing 151–175 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7196934 | Non-volatile memory with erase verify circuit having comparators indicating under-erasure, erasure, and over-erasure of memory cells | — | 2007-03-27 |
| 7186569 | Conductive memory stack with sidewall | Darrell Rinerson, Steve Kuo-Ren Hsia, Wayne Kinney, Steven W. Longcor, Emond Ward | 2007-03-06 |
| 7167396 | Erase verify for nonvolatile memory using reference current-to-voltage converters | — | 2007-01-23 |
| 7158397 | Line drivers that fits within a specified line pitch | Darrell Rinerson | 2007-01-02 |
| 7155589 | Permanent memory block protection in a flash memory device | See Kit Leong | 2006-12-26 |
| 7149108 | Memory array of a non-volatile RAM | Darrell Rinerson | 2006-12-12 |
| 7149107 | Providing a reference voltage to a cross point memory array | Darrell Rinerson | 2006-12-12 |
| 7133323 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Vinod Lakhani, Mathew L. Adsitt | 2006-11-07 |
| 7130239 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Vinod Lakhani, Mathew L. Adsitt | 2006-10-31 |
| 7126841 | Non-volatile memory with a single transistor and resistive memory element | Darrell Rinerson | 2006-10-24 |
| 7123513 | Erase verify for non-volatile memory using a reference current-to-voltage converter | — | 2006-10-17 |
| 7123516 | Erase verify for nonvolatile memory using bitline/reference current-to-voltage converters | — | 2006-10-17 |
| 7120889 | Integrated circuit schematics and layouts | Adriana Ababei | 2006-10-10 |
| 7107554 | Line width check in layout database | Adriana Ababei | 2006-09-12 |
| 7099179 | Conductive memory array having page mode and burst mode write capability | Darrell Rinerson | 2006-08-29 |
| 7095644 | Conductive memory array having page mode and burst mode read capability | Darrell Rinerson | 2006-08-22 |
| 7095643 | Re-writable memory with multiple memory layers | Darrell Rinerson, Wayne Kinney, Steven W. Longcor, Edmond R. Ward | 2006-08-22 |
| 7082052 | Multi-resistive state element with reactive metal | Darrell Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor +2 more | 2006-07-25 |
| 7079442 | Layout of driver sets in a cross point memory array | Darrell Rinerson, Steven W. Longcor, Wayne Kinney, Edmond R. Ward | 2006-07-18 |
| 7075817 | Two terminal memory array having reference cells | Darrell Rinerson, Steven W. Longcor | 2006-07-11 |
| 7071008 | Multi-resistive state material that uses dopants | Darrell Rinerson, Wayne Kinney, Steven W. Longcor, Edmond R. Ward, Steve Kuo-Ren Hsia | 2006-07-04 |
| 7067862 | Conductive memory device with conductive oxide electrodes | Darrell Rinerson, Steven W. Longcor, Steve Kuo-Ren Hsia, Wayne Kinney, Edmond R. Ward | 2006-06-27 |
| 7057935 | Erase verify for non-volatile memory | — | 2006-06-06 |
| 7057914 | Cross point memory array with fast access time | Darrell Rinerson, Steven W. Longcor, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia | 2006-06-06 |
| 7055115 | Line width check in layout database | Adriana Ababei | 2006-05-30 |