Issued Patents All Time
Showing 126–150 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7633790 | Multi-resistive state memory device with conductive oxide electrodes | Darrel Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor +2 more | 2009-12-15 |
| 7569414 | CMOS imager with integrated non-volatile memory | — | 2009-08-04 |
| 7538338 | Memory using variable tunnel barrier widths | Darrell Rinerson, Wayne Kinney, Edmond R. Ward | 2009-05-26 |
| 7528405 | Conductive memory stack with sidewall | Darrell Rinerson, Steve Kuo-Ren Hsia, Steven W. Longcor | 2009-05-05 |
| 7505347 | Method for sensing a signal in a two-terminal memory array having leakage current | Darrell Rinerson, Chang Hua Siau | 2009-03-17 |
| 7457997 | Apparatus and method for detecting over-programming condition in multistate memory device | Robert Norman | 2008-11-25 |
| 7457147 | Two terminal memory array having reference cells | Darrell Rinerson, Steven W. Longcor | 2008-11-25 |
| 7437647 | Mode entry circuit and method | — | 2008-10-14 |
| 7436723 | Method for two-cycle sensing in a two-terminal memory array having leakage current | Darrell Rinerson, Chang Hua Siau | 2008-10-14 |
| 7428714 | Line width error check | Adriana Ababei | 2008-09-23 |
| 7394679 | Multi-resistive state element with reactive metal | Darrell Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor +2 more | 2008-07-01 |
| 7382645 | Two terminal memory array having reference cells | Darrell Rinerson, Steven W. Longcor | 2008-06-03 |
| 7382644 | Two terminal memory array having reference cells | Darrell Rinerson, Steven W. Longcor | 2008-06-03 |
| 7379364 | Sensing a signal in a two-terminal memory array having leakage current | Chang Hua Siau, Darrell Rinerson | 2008-05-27 |
| 7372753 | Two-cycle sensing in a two-terminal memory array having leakage current | Darrell Rinerson, Chang Hua Siau | 2008-05-13 |
| 7330370 | Enhanced functionality in a two-terminal memory array | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Robert Norman | 2008-02-12 |
| 7327601 | Providing a reference voltage to a cross point memory array | Darrell Rinerson | 2008-02-05 |
| 7326979 | Resistive memory device with a treated interface | Darrell Rinerson, Wayne Kinney, John Sanchez, Steven W. Longcor, Steve Kuo-Ren Hsia +1 more | 2008-02-05 |
| 7251187 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Vinod Lakhani, Mathew L. Adsitt | 2007-07-31 |
| 7248515 | Non-volatile memory with test rows for disturb detection | — | 2007-07-24 |
| 7236399 | Method for erase-verifying a non-volatile memory capable of identifying over-erased and under-erased memory cells | — | 2007-06-26 |
| 7236400 | Erase verify for non-volatile memory using a bitline current-to-voltage converter | — | 2007-06-26 |
| 7230855 | Erase verify for non-volatile memory using bitline/reference current-to-voltage converters | — | 2007-06-12 |
| 7227775 | Two terminal memory array having reference cells | Darrell Rinerson, Steven W. Longcor | 2007-06-05 |
| 7227767 | Cross point memory array with fast access time | Darrell Rinerson | 2007-06-05 |