Issued Patents All Time
Showing 51–75 of 281 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10594322 | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells | Mou-Shiung Lin | 2020-03-17 |
| 10523210 | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells | Mou-Shiung Lin | 2019-12-31 |
| 10489544 | Logic drive based on standard commodity FPGA IC chips | Mou-Shiung Lin | 2019-11-26 |
| 10447274 | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells | Mou-Shiung Lin | 2019-10-15 |
| 9612615 | Integrated circuit chip using top post-passivation technology and bottom structure technology | Mou-Shiung Lin, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu | 2017-04-04 |
| 9369175 | Low fabrication cost, high performance, high reliability chip scale package | Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin | 2016-06-14 |
| 9153555 | Method of wire bonding over active area of a semiconductor circuit | Ying-Chih Chen, Mou-Shiung Lin | 2015-10-06 |
| 9142527 | Method of wire bonding over active area of a semiconductor circuit | Ying-Chih Chen, Mou-Shiung Lin | 2015-09-22 |
| 9136246 | Integrated chip package structure using silicon substrate and method of manufacturing the same | Mou-Shiung Lin, Ching-Cheng Huang | 2015-09-15 |
| 9030029 | Chip package with die and substrate | Mou-Shiung Lin, Ching-Cheng Huang | 2015-05-12 |
| 9018774 | Chip package | Ching-Cheng Huang, Mou-Shiung Lin | 2015-04-28 |
| 8912666 | Structure and manufacturing method of chip scale package | Ching-Cheng Huang, Mou-Shiung Lin | 2014-12-16 |
| 8890336 | Cylindrical bonding structure and method of manufacture | Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo | 2014-11-18 |
| 8853754 | Image and light sensor chip packages | Mou-Shiung Lin | 2014-10-07 |
| 8809951 | Chip packages having dual DMOS devices with power management integrated circuits | Mou-Shiung Lin | 2014-08-19 |
| 8804360 | System-in packages | Mou-Shiung Lin | 2014-08-12 |
| 8748227 | Method of fabricating chip package | Ching-Cheng Huang, Mou-Shiung Lin | 2014-06-10 |
| 8742580 | Method of wire bonding over active area of a semiconductor circuit | Ying-Chih Chen, Mou-Shiung Lin | 2014-06-03 |
| 8618580 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Chien-Kang Chou | 2013-12-31 |
| 8592977 | Integrated circuit (IC) chip and method for fabricating the same | Chiu-Ming Chou | 2013-11-26 |
| 8546947 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2013-10-01 |
| 8535976 | Method for fabricating chip package with die and substrate | Mou-Shiung Lin, Ching-Cheng Huang | 2013-09-17 |
| 8503186 | System-in packages | Mou-Shiung Lin | 2013-08-06 |
| 8492900 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2013-07-23 |
| 8492870 | Semiconductor package with interconnect layers | Mou-Shiung Lin, Ching-Cheng Huang | 2013-07-23 |