Issued Patents All Time
Showing 51–70 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6350700 | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure | Richard Schinella, Philippe Schoenborn | 2002-02-26 |
| 6346490 | Process for treating damaged surfaces of low k carbon doped silicon oxide dielectric material after plasma etching and plasma cleaning steps | Wei-Jen Hsia, Alex Kabansky | 2002-02-12 |
| 6297555 | Method to obtain a low resistivity and conformity chemical vapor deposition titanium film | Joe W. Zhao, Wei-Jen Hsia | 2001-10-02 |
| 6239499 | Consistent alignment mark profiles on semiconductor wafers using PVD shadowing | Joe W. Zhao, Shumay X. Dou | 2001-05-29 |
| 6232658 | Process to prevent stress cracking of dielectric films on semiconductor wafers | Wei-Jen Hsia, Joe W. Zhao | 2001-05-15 |
| 6204192 | Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures | Joe W. Zhao, Wei-Jen Hsia | 2001-03-20 |
| 6204550 | Method and composition for reducing gate oxide damage during RF sputter clean | Zhihai Wang, Wei-Jen Hsia | 2001-03-20 |
| 6028015 | Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption | Zhihai Wang, Joe W. Zhao | 2000-02-22 |
| 5994211 | Method and composition for reducing gate oxide damage during RF sputter clean | Zhihai Wang, Wei-Jen Hsia | 1999-11-30 |
| 5994775 | Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same | Joe W. Zhao | 1999-11-30 |
| 5956613 | Method for improvement of TiN CVD film quality | Joe W. Zhao | 1999-09-21 |
| 5953631 | Low stress, highly conformal CVD metal thin film | Joe W. Zhao | 1999-09-14 |
| 5933757 | Etch process selective to cobalt silicide for formation of integrated circuit structures | Stephanie A. Yoshikawa | 1999-08-03 |
| 5926720 | Consistent alignment mark profiles on semiconductor wafers using PVD shadowing | Joe W. Zhao, Shumay X. Dou | 1999-07-20 |
| 5902129 | Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers | Stephanie A. Yoshikawa, Zhihai Wang | 1999-05-11 |
| 5895267 | Method to obtain a low resistivity and conformity chemical vapor deposition titanium film | Joe W. Zhao, Wei-Jen Hsia | 1999-04-20 |
| 5789028 | Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride | Joe W. Zhao, Wei-Jen Hsia | 1998-08-04 |
| 5770520 | Method of making a barrier layer for via or contact opening of integrated circuit structure | Joe W. Zhao, Zhihai Wang | 1998-06-23 |
| 5660682 | Plasma clean with hydrogen gas | Joe W. Zhao, Zhihai Wang | 1997-08-26 |
| 5635244 | Method of forming a layer of material on a wafer | Mark Mayeda, Joe W. Zhao | 1997-06-03 |