Issued Patents All Time
Showing 26–50 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8539009 | Parallel true random number generator architecture | Pavel A. Aliseychik, Oleg Izyumin, Ilya V. Neznanov, Pavel A. Panteleev | 2013-09-17 |
| 8527851 | System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors | Alexander E. Andreev, Pavel A. Aliseychik, Ilya V. Neznanov, Pavel A. Panteleev | 2013-09-03 |
| 8397143 | BCH or reed-solomon decoder with syndrome modification | Ilya V. Neznanov, Pavel A. Panteleev, Pavel A. Aliseychik, Andrey P. Sokolov | 2013-03-12 |
| 8365054 | Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder | Andrey P. Sokolov, Pavel A. Panteleev, Ilya V. Neznanov, Pavel A. Aliseychik | 2013-01-29 |
| 8286060 | Scheme for erasure locator polynomial calculation in error-and-erasure decoder | Pavel A. Panteleev, Alexander E. Andreev, Ilya V. Neznanov, Pavel A. Aliseychik | 2012-10-09 |
| 8209589 | Reed-solomon decoder with a variable number of correctable errors | Alexandre Andreev, Ilya V. Neznanov, Pavel A. Panteleev | 2012-06-26 |
| 8181096 | Configurable Reed-Solomon decoder based on modified Forney syndromes | Alexander E. Andreev, Ilya V. Neznanov, Pavel A. Panteleev | 2012-05-15 |
| 8176397 | Variable redundancy reed-solomon encoder | Pavel A. Panteleev, Alexandre Andreev, Ilya V. Neznanov | 2012-05-08 |
| 7823050 | Low area architecture in BCH decoder | Alexander E. Andreev, Ilya V. Neznanov, Pavel A. Panteleev, Sergei B. Gashkov | 2010-10-26 |
| 7568175 | Ramptime propagation on designs with cycles | Andrej A. Zolotykh, Alexei V. Galatenko, Ilya Lyalin | 2009-07-28 |
| 7496870 | Method of selecting cells in logic restructuring | Iliya V. Lyalin, Andrej A. Zolotykh, Alexei V. Galatenko | 2009-02-24 |
| 7401313 | Method and apparatus for controlling congestion during integrated circuit design resynthesis | Alexei V. Galatenko, Iliya V. Lyalin | 2008-07-15 |
| 7398486 | Method and apparatus for performing logical transformations for global routing | Alexei V. Galatenko, Andrej A. Zolotykh | 2008-07-08 |
| 7257791 | Multiple buffer insertion in global routing | Alexei V. Galatenko, Andrej A. Zolotykh, Iliya V. Lyalin | 2007-08-14 |
| 7246336 | Ramptime propagation on designs with cycles | Andrej A. Zolotykh, Alexei V. Galatenko, Ilya Lyalin | 2007-07-17 |
| 7146591 | Method of selecting cells in logic restructuring | Iliya V. Lyalin, Andrej A. Zolotykh, Alexei V. Galatenko | 2006-12-05 |
| 7111267 | Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths | Iliya V. Lyalin, Alexei V. Galatenko, Andrej A. Zolotykh | 2006-09-19 |
| 7103865 | Process and apparatus for placement of megacells in ICs design | Alexei V. Galatenko, Valeriy B. Kudryavtsev | 2006-09-05 |
| 7003739 | Method and apparatus for finding optimal unification substitution for formulas in technology library | Alexander S. Podkolzin, Alexei V. Galatenko | 2006-02-21 |
| 6868536 | Method to find boolean function symmetries | Andrej A. Zolotykh, Aiguo Lu | 2005-03-15 |
| 6845495 | Multidirectional router | Alexandre Andreev, Ranko Scepanovic | 2005-01-18 |
| 6810515 | Process of restructuring logics in ICs for setup and hold time optimization | Aiguo Lu, Ivan Pavisic, Andrej A. Zolotykh | 2004-10-26 |
| 6701493 | Floor plan tester for integrated circuit design | Andrej A. Zolotykh, Ivan Pavisic, Aiguo Lu | 2004-03-02 |
| 6701503 | Overlap remover manager | Andrey Nikitin, Andrej A. Zolotykh | 2004-03-02 |
| 6681373 | Method and apparatus for dynamic buffer and inverter tree optimization | Andrej A. Zolotykh, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2004-01-20 |