Issued Patents All Time
Showing 26–50 of 258 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12289104 | Ferroelectric or paraelectric based low power multiplier array | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2025-04-29 |
| 12289894 | Method of fabricating transistors and stacked planar capacitors for memory and logic applications | Rajeev Kumar Dokania, Noriyuki Sato, Rafael Rios, Niloy Mukherjee, Somilkumar J. Rathi +2 more | 2025-04-29 |
| 12283571 | Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor | Rajeev Kumar Dokania, Sasikanth Manipatruni, Debo Olaosebikan | 2025-04-22 |
| 12283955 | Majority or minority based low power checkerboard carry save multiplier with inverted multiplier cells | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2025-04-22 |
| 12274071 | Capacitor integrated with a transistor for logic and memory applications | Mauricio Manfrini, Noriyuki Sato, James David Clarkson, Abel Fernandez, Somilkumar J. Rathi +4 more | 2025-04-08 |
| 12272675 | Method of forming 3D stacked compute and memory with copper pillars | Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2025-04-08 |
| 12265494 | Multi-die mapping matrix multiplication | Rajeev Kumar Dokania, Ananda Samajdar, Sasikanth Manipatruni | 2025-04-01 |
| 12262541 | Trench capacitors with shared electrode | Noriyuki Sato, Tanay Gosavi, Rafael Rios, Niloy Mukherjee, Mauricio Manfrini +3 more | 2025-03-25 |
| 12262543 | High density ferroelectric random access memory (FeRAM) devices and methods of fabrication | Debraj Guhabiswas, Maria Isabel Perez, Jason Y. Wu, James David Clarkson, Gabriel Antonio Paulius Velarde +4 more | 2025-03-25 |
| 12243797 | 3D stack of split graphics processing logic dies | Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2025-03-04 |
| 12238935 | Embedded memory adjacent to non-memory | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-02-25 |
| 12218045 | Stacked planar capacitors based multi-function linear threshold gate with input based adaptive threshold | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2025-02-04 |
| 12212321 | Non-linear polar material based flip-flop | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2025-01-28 |
| 12200941 | Pillar capacitor and method of fabricating such | Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2025-01-14 |
| 12190946 | Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell | Rajeev Kumar Dokania, Mustansir Yunus Mukadam, Tanay Gosavi, James David Clarkson, Neal Reynolds +1 more | 2025-01-07 |
| 12171103 | Multi-input threshold gate having stacked and folded non-planar capacitors | Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-12-17 |
| 12166011 | Method of forming an artificial intelligence processor with three-dimensional stacked memory | Rajeev Kumar Dokania, Sasikanth Manipatruni, Debo Olaosebikan | 2024-12-10 |
| 12155383 | Reset mechanism for an adder or a multiplier having paraelectric material | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-11-26 |
| 12147747 | Area oriented logic synthesis | Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania | 2024-11-19 |
| 12147941 | Iterative monetization of precursor in process development of non-linear polar material and devices | Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Somilkumar J. Rathi +3 more | 2024-11-19 |
| 12142310 | Method of fabricating pedestal based memory devices using pocket integration | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-11-12 |
| 12137574 | Integration of ferroelectric memory devices having stacked electrodes with transistors | Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Gaurav Thareja | 2024-11-05 |
| 12126339 | Apparatus with selectable majority gate and combinational logic gate outputs | Sasikanth Manipatruni, Rafael Rios, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania +1 more | 2024-10-22 |
| 12118327 | Ripple carry adder with inverted ferroelectric or paraelectric based adders | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2024-10-15 |
| 12118330 | Low power multiplier with non-linear polar material based reset mechanism with sequential reset | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-10-15 |