Issued Patents All Time
Showing 76–100 of 258 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11997853 | 1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset | Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-05-28 |
| 11996438 | Pocket flow for trench capacitors integrated with planar capacitors on a same substrate and method of fabrication | Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Tanay Gosavi +3 more | 2024-05-28 |
| 11985832 | Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications | Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Tanay Gosavi +3 more | 2024-05-14 |
| 11985831 | Multi-function threshold gate with input based adaptive threshold and with stacked non-planar ferroelectric capacitors | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-05-14 |
| 11979148 | Asynchronous consensus circuit with stacked linear or paraelectric planar capacitors | Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-05-07 |
| 11978762 | Planar capacitors with non-linear polar material staggered on a shared electrode | Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-05-07 |
| 11967954 | Majority or minority logic gate with non-linear input capacitors without reset | Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-04-23 |
| 11961877 | Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures | Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Tanay Gosavi +3 more | 2024-04-16 |
| 11955512 | Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication | Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Tanay Gosavi +3 more | 2024-04-09 |
| 11955153 | Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset | Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-04-09 |
| 11942133 | Pedestal-based pocket integration process for embedded memory | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-03-26 |
| 11922105 | Computer-aided design tool for minimum gate count initialization | Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania | 2024-03-05 |
| 11908704 | Method of fabricating a perovskite-material based planar capacitor using rapid thermal annealing (RTA) methodologies | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2024-02-20 |
| 11910618 | Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors | Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-02-20 |
| 11909391 | Asynchronous completion tree circuit using multi-function threshold gate with input based adaptive threshold | Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-02-20 |
| 11903219 | Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors | Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-02-13 |
| 11901891 | Asynchronous consensus circuit with stacked ferroelectric planar capacitors | Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-02-13 |
| 11899613 | Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging | Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-02-13 |
| 11894417 | Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2024-02-06 |
| 11888479 | Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-30 |
| 11875836 | Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing | Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania | 2024-01-16 |
| 11869928 | Dual hydrogen barrier layer for memory devices | Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more | 2024-01-09 |
| 11869843 | Integrated trench and via electrode for memory device applications and methods of fabrication | Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more | 2024-01-09 |
| 11869562 | Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion | Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania | 2024-01-09 |
| 11871583 | Ferroelectric memory devices | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-09 |