Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10783304 | System, method, and computer program product for displaying debugging during a formal verification | Thiago Radicchi Roque, Stefan Staber | 2020-09-22 |
| 10635768 | System, method, and computer program product for displaying multiple traces while debugging during a formal verification | Thiago Radicchi Roque, Chien-Liang Lin, Guilherme Henrique de Sousa Santos | 2020-04-28 |
| 10409945 | Methods, systems, and computer program product for connectivity verification of electronic designs | Georgia Penido Safe, Guilherme Henrique de Sousa Santos, Adriana Cassia Rossi de Almeida Braz | 2019-09-10 |
| 10380295 | Methods, systems, and articles of manufacture for X-behavior verification of an electronic design | Georgia Penido Safe | 2019-08-13 |
| 10331547 | System, method, and computer program product for capture and reuse in a debug workspace | Chien-Liang Lin | 2019-06-25 |
| 10162917 | Method and system for implementing selective transformation for low power verification | Fabiano Peixoto, Benjamin Chen, Björn Håkan Hjort | 2018-12-25 |
| 10094875 | Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design | Chien-Liang Lin, Andrea Iabrudi Tavares | 2018-10-09 |
| 9928328 | Method and system for automated debugging of a device under test | Ynon Cohen, Tal Tabakman, Yonatan Ashkenazi, Nadav Chazan, Gavriel Leshem | 2018-03-27 |
| 9734278 | Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designs | Victor Markus Purri, Guilherme Henrique de Sousa Santos, Marcus Vincius da Mata Gomes | 2017-08-15 |
| 9659142 | Methods, systems, and articles of manufacture for trace warping for electronic designs | Claudionor Coelho, Thiago Radicchi Roque | 2017-05-23 |
| 9477802 | Isolating differences between revisions of a circuit design | Rajeev Ranjan, Kathryn Drews Kranen, Beth C. Isaksen, Georgia Penido Safe | 2016-10-25 |
| 9081927 | Manipulation of traces for debugging a circuit design | Claudionor Coelho, Chien-Liang Lin | 2015-07-14 |
| 8990745 | Manipulation of traces for debugging behaviors of a circuit design | Claudionor Coelho, Chien-Liang Lin | 2015-03-24 |
| 8984461 | Visualization constraints for circuit designs | Chien-Liang Lin | 2015-03-17 |
| 8863049 | Constraining traces in formal verification | Lars Lundgren, Ziyad Hanna, Kathryn Drews Kranen, Lawrence Loh | 2014-10-14 |
| 8831925 | Indexing behaviors and recipes of a circuit design | Kathryn Drews Kranen, Rajeev Ranjan, Lawrence Loh, Beth C. Isaksen, Yann Alain Antonioli +1 more | 2014-09-09 |
| 8731894 | Indexing behaviors and recipes of a circuit design | Kathryn Drews Kranen, Rajeev Ranjan, Lawrence Loh, Beth C. Isaksen, Yann Alain Antonioli +1 more | 2014-05-20 |
| 8630824 | Comprehending waveforms of a circuit design | Kathryn Drews Kranen, Rajeev Ranjan, Beth C. Isaksen, Karl Stefan Esbjörner, Craig Franklin Deaton | 2014-01-14 |
| 8527911 | Comprehending a circuit design | Kathryn Drews Kranen, Rajeev Ranjan, Georgia Penido Safe, Claudionor Coelho, Yann Alain Antonioli | 2013-09-03 |
| 8205187 | Generalizing and inferring behaviors of a circuit design | Claudionor Coelho, Harry D. Foster, Rajeev Ranjan, Kathryn Drews Kranen, Georgia Penido Safe | 2012-06-19 |
| 7895552 | Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction | Vigyan Singhal, Soe Myint, Howard Wong-Toi | 2011-02-22 |
| 7647572 | Managing formal verification complexity of designs with multiple related counters | Lawrence Loh, Vigyan Singhal, Howard Wong-Toi | 2010-01-12 |
| 7506288 | Interactive analysis and debugging of a circuit design during functional verification of the circuit design | Mohit Jain | 2009-03-17 |
| 7437694 | System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design | Lawrence Loh, Soe Myint | 2008-10-14 |
| 7421668 | Meaningful visualization of properties independent of a circuit design | Yann Alain Antonioli | 2008-09-02 |