CI

Chung-Wah Norris Ip

JA Jasper Design Automation: 18 patents #1 of 35Top 3%
CS Cadence Design Systems: 12 patents #85 of 2,263Top 4%
📍 Cupertino, CA: #520 of 6,989 inventorsTop 8%
🗺 California: #17,156 of 386,348 inventorsTop 5%
Overall (All Time): #124,630 of 4,157,543Top 3%
30
Patents All Time

Issued Patents All Time

Showing 26–30 of 30 patents

Patent #TitleCo-InventorsDate
7418678 Managing formal verification complexity of designs with counters Lawrence Loh, Vigyan Singhal, Howard Wong-Toi 2008-08-26
7237208 Managing formal verification complexity of designs with datapaths Lawrence Loh, Howard Wong-Toi, Harry D. Foster 2007-06-26
7159198 System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model Lawrence Loh, Vigyan Singhal, Howard Wong-Toi, Soe Myint 2007-01-02
7065726 System and method for guiding and optimizing formal verification for a circuit design Vigyan Singhal, Joseph E. Higgins, Howard Wong-Toi 2006-06-20
6915248 Method and apparatus for transforming test stimulus 2005-07-05