Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10204201 | Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques | Artur Melo Mota Costa, Breno Rodrigues Guimaraes, Fabiano Peixoto, Andrea Iabrudi Tavares | 2019-02-12 |
| 9934410 | Security data path verification | Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Claudionor Coelho | 2018-04-03 |
| 9922209 | Security data path verification | Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Claudionor Coelho | 2018-03-20 |
| 9633151 | Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths | Xiaoyang Sun, Marcus Vinicius da Mata Gomes, Andrea Iabrudi Tavares, Fabiano Peixoto | 2017-04-25 |
| 9633153 | Method, system, and computer program product for verifying an electronic design using stall prevention requirements of electronic circuit design models of the electronic design | Sergey Khaikin | 2017-04-25 |
| 9594861 | Method and system to perform equivalency checks | Antonio Celso Caldeira, Jr., Marcus Vinicius da Mata Gomes | 2017-03-14 |
| 9449196 | Security data path verification | Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Claudionor Coelho | 2016-09-20 |
| 9104824 | Power aware retention flop list analysis and modification | Barbara Jobstmann, Antonio Celso Caldeira, Jr., Jamil Raja Mazzawi | 2015-08-11 |
| 8954904 | Veryifing low power functionality through RTL transformation | Barbara Jobstmann, Antonio Celso Caldeira, Jr., Jamil Raja Mazzawi | 2015-02-10 |
| 8863049 | Constraining traces in formal verification | Lars Lundgren, Ziyad Hanna, Chung-Wah Norris Ip, Kathryn Drews Kranen | 2014-10-14 |
| 8831925 | Indexing behaviors and recipes of a circuit design | Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Ranjan, Beth C. Isaksen, Yann Alain Antonioli +1 more | 2014-09-09 |
| 8731894 | Indexing behaviors and recipes of a circuit design | Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Ranjan, Beth C. Isaksen, Yann Alain Antonioli +1 more | 2014-05-20 |
| 8381148 | Formal verification of deadlock property | Xiaoyang Sun | 2013-02-19 |
| 7647572 | Managing formal verification complexity of designs with multiple related counters | Chung-Wah Norris Ip, Vigyan Singhal, Howard Wong-Toi | 2010-01-12 |
| 7437694 | System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design | Chung-Wah Norris Ip, Soe Myint | 2008-10-14 |
| 7418678 | Managing formal verification complexity of designs with counters | Chung-Wah Norris Ip, Vigyan Singhal, Howard Wong-Toi | 2008-08-26 |
| 7237208 | Managing formal verification complexity of designs with datapaths | Chung-Wah Norris Ip, Howard Wong-Toi, Harry D. Foster | 2007-06-26 |
| 7159198 | System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model | Chung-Wah Norris Ip, Vigyan Singhal, Howard Wong-Toi, Soe Myint | 2007-01-02 |