Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11580284 | System, method, and computer program product for finding and analyzing deadlock conditions associated with the formal verification of an electronic circuit design | Craig Franklin Deaton, Christopher William Komar | 2023-02-14 |
| 11520964 | Method and system for assertion-based formal verification using unique signature values | Ahmad S. Abo Foul, Björn Håkan Hjort, Habeeb Farah, Eran Talmor, Paula Selegato Mathias | 2022-12-06 |
| 11514219 | System and method for assertion-based formal verification using cached metadata | Ahmad S. Abo Foul, Björn Håkan Hjort, Habeeb Farah | 2022-11-29 |
| 11507720 | Systems and methods for signal observability rating | Matheus Nogueira Fonseca, Thamara Karen Cunha Andrade, Breno Rodrigues Guimaraes | 2022-11-22 |
| 10380312 | System, method, and computer program product for analyzing formal constraint conflicts | Craig Franklin Deaton | 2019-08-13 |
| 10176285 | System, method, and computer program product for property violation comprehension | — | 2019-01-08 |
| 10108767 | Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design | Victor Markus Purri, Michael D. Pedneau, Pradeep Goyal | 2018-10-23 |
| 9372949 | Guided exploration of circuit design states | Ziyad Hanna, Craig Franklin Deaton, Kathryn Drews Kranen, Björn Håkan Hjort | 2016-06-21 |
| 9246771 | Cloud communication layer for a user device | Erik Artur Greisson, Linda Tolj | 2016-01-26 |
| 8863049 | Constraining traces in formal verification | Ziyad Hanna, Chung-Wah Norris Ip, Kathryn Drews Kranen, Lawrence Loh | 2014-10-14 |