Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11520964 | Method and system for assertion-based formal verification using unique signature values | Ahmad S. Abo Foul, Lars Lundgren, Björn Håkan Hjort, Eran Talmor, Paula Selegato Mathias | 2022-12-06 |
| 11514219 | System and method for assertion-based formal verification using cached metadata | Ahmad S. Abo Foul, Lars Lundgren, Björn Håkan Hjort | 2022-11-29 |
| 11080448 | Method and system for formal bug hunting | Yaron Schiller, Guy Wolfovitz | 2021-08-03 |
| 11023357 | Method and system for sequential equivalence checking | Ayman Hanna, Karam Abdelkader, Doron Bustan, Thiago Radicchi Roque, Felipe Althoff | 2021-06-01 |
| 10984161 | System, method, and computer program product for sequential equivalence checking in formal verification | Rajdeep Mukherjee, Ravi Prakash, Benjamin Chen, Ziyad Hanna | 2021-04-20 |
| 10983758 | System, method, and computer program product for automatically inferring case-split hints in equivalence checking of an electronic design | Rajdeep Mukherjee, Benjamin Chen, Ziyad Hanna | 2021-04-20 |
| 10853546 | Method and system for sequential equivalence checking | Yaron Schiller, Almothana Sirhan, Karam Abdelkader, Thiago Radicchi Roque | 2020-12-01 |
| 10789404 | System, method, and computer program product for generating a formal verification model | Rajdeep Mukherjee, Benjamin Chen, Ziyad Hanna | 2020-09-29 |
| 10782767 | System, method, and computer program product for clock gating in a formal verification | Karam Abd Elkader, Doron Bustan, Yaron Schiller | 2020-09-22 |
| 10546083 | System, method, and computer program product for improving coverage accuracy in formal verification | Amit Verma, Suyash Kumar | 2020-01-28 |
| 10452798 | System, method, and computer program product for filtering one or more failures in a formal verification | Nizar Hanna, Almothana Sarhan, Doron Bustan | 2019-10-22 |
| 9177089 | Formal verification coverage metrics for circuit design properties | Ziyad Hanna, Per Anders M. Franzen, Ross M. Weber, Rajeev Ranjan | 2015-11-03 |
| 9158874 | Formal verification coverage metrics of covered events for circuit design properties | Rajeev Ranjan, Ross M. Weber, Ziyad Hanna | 2015-10-13 |
| 8826201 | Formal verification coverage metrics for circuit design properties | Ziyad Hanna, Per Anders M. Franzen, Ross M. Weber, Rajeev Ranjan | 2014-09-02 |
| 7346864 | Logic design development tool and method | Johny Srouji, Yulik Feldman, Gila Kamhi, Jacob Katz, Yossef Levy | 2008-03-18 |