YS

Yaron Schiller

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
Overall (All Time): #1,158,237 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
11151295 Method and system for sequential equivalence checking Doron Bustan, Karam Abdelkader 2021-10-19
11080448 Method and system for formal bug hunting Guy Wolfovitz, Habeeb Farah 2021-08-03
10853546 Method and system for sequential equivalence checking Almothana Sirhan, Karam Abdelkader, Habeeb Farah, Thiago Radicchi Roque 2020-12-01
10782767 System, method, and computer program product for clock gating in a formal verification Karam Abd Elkader, Doron Bustan, Habeeb Farah 2020-09-22