VP

Victor Markus Purri

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
JA Jasper Design Automation: 1 patents #22 of 35Top 65%
📍 Sunnyvale, CA: #4,767 of 14,302 inventorsTop 35%
🗺 California: #106,790 of 386,348 inventorsTop 30%
Overall (All Time): #984,138 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
10108767 Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design Michael D. Pedneau, Lars Lundgren, Pradeep Goyal 2018-10-23
9934410 Security data path verification Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Coelho 2018-04-03
9922209 Security data path verification Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Coelho 2018-03-20
9734278 Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designs Guilherme Henrique de Sousa Santos, Chung-Wah Norris Ip, Marcus Vincius da Mata Gomes 2017-08-15
9449196 Security data path verification Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Coelho 2016-09-20