GS

Georgia Penido Safe

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
JA Jasper Design Automation: 2 patents #16 of 35Top 50%
📍 Felixlândia, BR: #3 of 84 inventorsTop 4%
Overall (All Time): #714,891 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
10990734 Partition-based circuit analysis and verification Vincent Gregory Reynolds, Adriana Cassia Rossi de Almeida Braz, Julio Alexandre Silva Rezende 2021-04-27
10956640 System, method, and computer program product for determining suitability for formal verification Mirlaine Aparecida Crepalde, Yumi Monma, Felipe Althoff, Fernanda Augusta Braga, Lucas Martins Chaves +3 more 2021-03-23
10409945 Methods, systems, and computer program product for connectivity verification of electronic designs Chung-Wah Norris Ip, Guilherme Henrique de Sousa Santos, Adriana Cassia Rossi de Almeida Braz 2019-09-10
10380295 Methods, systems, and articles of manufacture for X-behavior verification of an electronic design Chung-Wah Norris Ip 2019-08-13
9477802 Isolating differences between revisions of a circuit design Chung-Wah Norris Ip, Rajeev Ranjan, Kathryn Drews Kranen, Beth C. Isaksen 2016-10-25
8527911 Comprehending a circuit design Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Ranjan, Claudionor Coelho, Yann Alain Antonioli 2013-09-03
8205187 Generalizing and inferring behaviors of a circuit design Claudionor Coelho, Chung-Wah Norris Ip, Harry D. Foster, Rajeev Ranjan, Kathryn Drews Kranen 2012-06-19