VR

Vincent Gregory Reynolds

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
Overall (All Time): #1,153,704 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
10990734 Partition-based circuit analysis and verification Georgia Penido Safe, Adriana Cassia Rossi de Almeida Braz, Julio Alexandre Silva Rezende 2021-04-27
10956640 System, method, and computer program product for determining suitability for formal verification Georgia Penido Safe, Mirlaine Aparecida Crepalde, Yumi Monma, Felipe Althoff, Fernanda Augusta Braga +3 more 2021-03-23
10586014 Method and system for verification using combined verification data Yael Kinderman, David R. Spatafore, Nili Segal, Yan Yagudayev 2020-03-10
10325042 Debugging failures in X-propagation logic circuit simulation Amit Sharma, Amit Aggarwal, Amit Dua, Manu Chopra, Abhishek Raheja 2019-06-18