DS

David R. Spatafore

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
UN Unisys: 2 patents #632 of 2,015Top 35%
📍 Maple Grove, MN: #342 of 1,211 inventorsTop 30%
🗺 Minnesota: #13,602 of 52,454 inventorsTop 30%
Overall (All Time): #926,373 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
11941335 Providing concise data for analyzing checker completeness Amit Verma, Yumi Monma, Suyash Kumar, Devank Jain 2024-03-26
10586014 Method and system for verification using combined verification data Yael Kinderman, Nili Segal, Yan Yagudayev, Vincent Gregory Reynolds 2020-03-10
10515169 System, method, and computer program product for computing formal coverage data compatible with dynamic verification Amit Verma, Anubhav Srivastava 2019-12-24
8032687 Method, system, and apparatus for supporting limited address mode memory access 2011-10-04
7895379 Logic controller having hard-coded control logic and programmable override control store entries Ross M. Weber 2011-02-22