Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JY

James Yamaguchi — 20 Patents

ISIrvine Sensors: 11 patents #2 of 64Top 4%
ISIsc8: 2 patents #3 of 15Top 20%
PIPfg Ip: 2 patents #3 of 11Top 30%
RARockwell Automation: 2 patents #1,811 of 4,211Top 45%
ACAprolase Development Co.: 1 patents #10 of 17Top 60%
Laguna Niguel, CA: #85 of 1,027 inventorsTop 9%
California: #29,208 of 386,348 inventorsTop 8%
Overall (All Time): #214,803 of 4,157,543Top 6%
20 Patents All Time
James Yamaguchi has been granted 20 US patents while listed as an inventor at Irvine Sensors. The first was granted in 1991 and the most recent in August 2017. James Yamaguchi ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list James Yamaguchi in Laguna Niguel, CA, US.

Patents per Year

Patents granted per year, 1991 to 2017Bar chart with a peak of 4 patents in 2004.peak 41991: 1 patents19911992: 1 patents1999: 1 patents19992000: 2 patents2003: 1 patents20032004: 4 patents2006: 1 patents20062007: 1 patents2008: 1 patents20082010: 1 patents2012: 1 patents20122013: 1 patents2014: 2 patents20142016: 1 patents2017: 1 patents2017

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9741680 Wire bond through-via structure and method Randy Bindrup, W. Eric Boyd, John Leon, Angel Pepe 2017-08-22
9431275 Wire bond through-via structure and method Randy Bindrup, W. Eric Boyd, John Leon, Angel Pepe 2016-08-30
8637140 Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the method W. Eric Boyd 2014-01-28
8637985 Anti-tamper wrapper interconnect method and a device Randy Bindrup, W. Eric Boyd 2014-01-28
8609473 Method for fabricating a neo-layer using stud bumped bare die Peter Lieu, Randy Bindrup, W. Eric Boyd 2013-12-17
RE43877 Method for precision integrated circuit die singulation using differential etch rates David Ludwig, Stewart Clark, W. Eric Boyd 2012-12-25
7786562 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias Volkan Ozguz, Angel Pepe, W. Eric Boyd, Douglas Albert, Andrew Camien 2010-08-31
7335576 Method for precision integrated circuit die singulation using differential etch rates Ludwig David, Stuart Clark, W. Eric Boyd 2008-02-26 $294,000
7239012 Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers Angel Pepe 2007-07-03 $1,327,000
7127807 Process of manufacturing multilayer modules Angel Pepe, Volkan Ozguz, Andrew Camien 2006-10-31 $335,000
6797537 Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers Angel Pepe 2004-09-28 $825,000
6784547 Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers Angel Pepe 2004-08-31 $729,000
6734370 Multilayer modules with flexible substrates Angel Pepe, Volkan Ozguz, Andrew Camien 2004-05-11 $1,013,000
6717061 Stacking of multilayer modules Angel Pepe, Volkan Ozguz, Andrew Camien 2004-04-06 $1,228,000
6560109 Stack of multilayer modules with heat-focusing metal layer Angel Pepe, Volkan Ozguz, Andrew Camien 2003-05-06 $435,000
6117704 Stackable layers containing encapsulated chips Volkan Ozguz, Andrew Camien 2000-09-12 $4,633,000
6072234 Stack of equal layer neo-chips containing encapsulated IC chips of different sizes Andrew Camien 2000-06-06 $7,389,000
5953588 Stackable layers containing encapsulated IC chips Andrew Camien 1999-09-14 $947,000
5123164 Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture Joseph M. Shaheen 1992-06-23 $4,164,000
5030499 Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture Joseph M. Shaheen 1991-07-09 $13,635,000